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![Tom Rini](/assets/img/avatar_default.png)
imx8: cleanup, fix warnings imx6ull: add VisionSOM SoM and EVK mx7ulp: fix warning due network, cleanup mx7dsabre: Fix dm probe pmic imx6: fixed for vining2000 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/639512296 -----BEGIN PGP SIGNATURE----- iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAl4m+D4PHHNiYWJpY0Bk ZW54LmRlAAoJECjE2NMq1et3hz0L/Rm48j733TNi7ZokndEr0+caMqk6PmJWE0Dy Uq4MwhhCkbPWP+uLQUY6yq64HXdx1fNaQnRzPiiaX2Ng9E/E9piOaYOKtKKs1j4q W+RiWfrGebgMemb8f2j4cot23KMUVk5/rv+EFn+oJkX7HD4ou/ikB4269/7b75Dg 1HsrsjWQq7Wsi4baVZZcfs92xTXltpkGEzgKFURt1tqU1TT1I+PX92aM/Df+qUYu ++DQTMr0kZ/yMlzxTvUJYN0KRkMnn6W07X/qQyU1YwioQmC1ZJ7zYBNZfoAG1XFs 0g6+XqfgLsDrTIeqz4/b98exXPdQqFNgRlUFnbVa0hZcehwxFUsb8J9edPl60k3r SYTOaIB8KuKstaNnaWJZm678THDrAXwpxSH9/ORRLX9tCnGBOY1Uy9Q+TJtpQ4K+ YGEeoKhMTMFcWxxZvpT75tvJMtcRdUw9rT+a5yuyD56NdYUmwiEw5c8hBa3vc26X C9P5jBxXbZIQQW67wMt0fFT1QdU5RA== =qKsO -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20200121' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx --------------------------------- imx8: cleanup, fix warnings imx6ull: add VisionSOM SoM and EVK mx7ulp: fix warning due network, cleanup mx7dsabre: Fix dm probe pmic imx6: fixed for vining2000 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/639512296
173 lines
3.3 KiB
C
173 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/arch/ddr.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <power/pmic.h>
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#include <power/bd71837.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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switch (boot_dev_spl) {
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC2;
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default:
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return BOOT_DEVICE_NONE;
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}
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}
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static void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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static int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@4b", &dev);
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if (ret == -ENODEV) {
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puts("No pmic\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* decrease RESET key long push time from the default 10s to 10ms */
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pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
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/* unlock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
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/* increase VDD_SOC to typical value 0.85v before first DRAM access */
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pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
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/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
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pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
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#ifndef CONFIG_IMX8M_LPDDR4
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/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
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pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
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#endif
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/* lock the PMIC regs */
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pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0) {
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printf("Failed to find clock node. Check device tree\n");
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hang();
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}
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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puts ("resetting ...\n");
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reset_cpu(WDOG1_BASE_ADDR);
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return 0;
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}
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