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---------------------------------

Browse Source 
imx8: cleanup, fix warnings
 imx6ull: add VisionSOM SoM and EVK
 mx7ulp: fix warning due network, cleanup
 mx7dsabre: Fix dm probe pmic
 imx6: fixed for vining2000
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/639512296
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Merge tag 'u-boot-imx-20200121' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

---------------------------------

imx8: cleanup, fix warnings
imx6ull: add VisionSOM SoM and EVK
mx7ulp: fix warning due network, cleanup
mx7dsabre: Fix dm probe pmic
imx6: fixed for vining2000

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/639512296
This commit is contained in:
Tom Rini 2020-01-21 08:36:50 -05:00
commit ad647690b1
33 changed files with 773 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/Makefile
View File

@ -677,6 +677,7 @@ dtb-$(CONFIG_MX6ULL) += \
imx6ull-colibri.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ull-somlabs-visionsom.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MX6) += \

4
arch/arm/dts/fsl-imx8-ca35.dtsi
View File

@ -18,6 +18,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
#cooling-cells = <2>;
};
A35_1: cpu@1 {
@ -26,6 +27,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
#cooling-cells = <2>;
};
A35_2: cpu@2 {
@ -34,6 +36,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
#cooling-cells = <2>;
};
A35_3: cpu@3 {
@ -42,6 +45,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
#cooling-cells = <2>;
};
A35_L2: l2-cache0 {

276
arch/arm/dts/imx6ull-somlabs-visionsom.dts Normal file
View File

@ -0,0 +1,276 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017-2019 SoMLabs
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"
/ {
model = "SoMLabs VisionSOM-6ULL";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
usr0 {
label = "usr0";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
usr1 {
label = "usr1";
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
usr2 {
label = "usr2";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
};
usr3 {
label = "usr3";
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg2>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&cpu0 {
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&gpc {
fsl,cpu_pupscr_sw2iso = <0x1>;
fsl,cpu_pupscr_sw = <0x0>;
fsl,cpu_pdnscr_iso2sw = <0x1>;
fsl,cpu_pdnscr_iso = <0x1>;
fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
/* 32kHz low power reference clock for WiFi */
MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
/* LED 0..3 */
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
>;
};
pinctrl_usb_otg2: usbotg2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
>;
};
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usbphy1 {
tx-d-cal = <0x5>;
};
&usbphy2 {
tx-d-cal = <0x5>;
};
&usdhc2 {
non-removable;
disable-wp;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,wdog_b;
};

2
arch/arm/dts/imx7ulp-evk.dts
View File

@ -156,7 +156,7 @@
pinctrl_backlight: backlight_grp {
fsl,pins = <
IMX7ULP_PAD_PTF2__PTF2 0x20100
IMX7ULP_PAD_PTF2__PTF2 0x20000
>;
};

4
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View File

@ -946,6 +946,10 @@
#define SNVS_LPCR_DPEN (0x20)
#define SNVS_LPCR_SRTC_ENV (0x1)
#define SRC_BASE_ADDR CMC1_RBASE
#define IRAM_BASE_ADDR OCRAM_0_BASE
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

10
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@ -47,7 +47,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
};
int fracpll_configure(enum pll_clocks pll, u32 freq)
static int fracpll_configure(enum pll_clocks pll, u32 freq)
{
int i;
u32 tmp, div_val;
@ -268,7 +268,7 @@ u32 imx_get_uartclk(void)
return 24000000U;
}
u32 decode_intpll(enum clk_root_src intpll)
static u32 decode_intpll(enum clk_root_src intpll)
{
u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
u32 main_div, pre_div, post_div, div;
@ -415,7 +415,7 @@ u32 decode_intpll(enum clk_root_src intpll)
return lldiv(freq, pre_div * (1 << post_div) * div);
}
u32 decode_fracpll(enum clk_root_src frac_pll)
static u32 decode_fracpll(enum clk_root_src frac_pll)
{
u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
u32 main_div, pre_div, post_div, k;
@ -480,7 +480,7 @@ u32 decode_fracpll(enum clk_root_src frac_pll)
65536 * pre_div * (1 << post_div));
}
u32 get_root_src_clk(enum clk_root_src root_src)
static u32 get_root_src_clk(enum clk_root_src root_src)
{
switch (root_src) {
case OSC_24M_CLK:
@ -524,7 +524,7 @@ u32 get_root_src_clk(enum clk_root_src root_src)
return 0;
}
u32 get_root_clk(enum clk_root_index clock_id)
static u32 get_root_clk(enum clk_root_index clock_id)
{
enum clk_root_src root_src;
u32 post_podf, pre_podf, root_src_clk;

13
arch/arm/mach-imx/mx6/Kconfig
View File

@ -540,6 +540,18 @@ config TARGET_SKSIMX6
bool "sks-imx6"
select SUPPORT_SPL
config TARGET_SOMLABS_VISIONSOM_6ULL
bool "visionsom-6ull"
select MX6ULL
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_MMC
select DM_SERIAL
select DM_THERMAL
imply CMD_DM
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
@ -694,6 +706,7 @@ source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"

2
arch/arm/mach-imx/mx7ulp/soc.c
View File

@ -118,6 +118,7 @@ void init_wdog(void)
disable_wdog(WDG2_RBASE);
}
#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
@ -175,6 +176,7 @@ void s_init(void)
#endif
return;
}
#endif
#ifndef CONFIG_ULP_WATCHDOG
void reset_cpu(ulong addr)

5
board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
View File

@ -108,11 +108,6 @@ int board_init(void)
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/

4
board/freescale/imx8mm_evk/README
View File

@ -15,12 +15,12 @@ branch: imx_4.19.35_1.0.0
$ make PLAT=imx8mm bl31
$ cp build/imx8mm/release/bl31.bin $(builddir)
Get the ddr and hdmi firmware
Get the ddr firmware
=============================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
$ chmod +x firmware-imx-8.0.bin
$ ./firmware-imx-8.0
$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
$ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
Build U-Boot
============

1
board/freescale/imx8mm_evk/imx8mm_evk.c
View File

@ -8,6 +8,7 @@
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;

4
board/freescale/imx8mm_evk/spl.c
View File

@ -39,7 +39,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
}
}
void spl_dram_init(void)
static void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
@ -84,7 +84,7 @@ int board_early_init_f(void)
return 0;
}
int power_init_board(void)
static int power_init_board(void)
{
struct udevice *dev;
int ret;

6
board/freescale/imx8qm_mek/imx8qm_mek.c
View File

@ -9,6 +9,7 @@
#include <errno.h>
#include <init.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
@ -100,11 +101,6 @@ int board_init(void)
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/

6
board/freescale/imx8qxp_mek/imx8qxp_mek.c
View File

@ -10,6 +10,7 @@
#include <init.h>
#include <linux/libfdt.h>
#include <fsl_esdhc_imx.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
@ -113,11 +114,6 @@ int board_init(void)
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/

2
board/freescale/mx7dsabresd/mx7dsabresd.c
View File

@ -264,7 +264,7 @@ int power_init_board(void)
struct udevice *dev;
int ret, dev_id, rev_id;
ret = pmic_get("pfuze3000@08", &dev);
ret = pmic_get("pfuze3000@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)

29
board/softing/vining_2000/vining_2000.c
View File

@ -146,7 +146,7 @@ static struct pmic *pfuze_init(unsigned char i2cbus)
return NULL;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
@ -427,8 +427,6 @@ void board_preboot_os(void)
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
static iomux_v3_cfg_t const pcie_pads[] = {
MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
@ -461,30 +459,13 @@ static void vining2000_spl_setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
int board_mmc_init(bd_t *bis)
{
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
u32 val;
u32 port;
val = readl(&src_regs->sbmr1);
if ((val & 0xc0) != 0x40) {
printf("Not boot from USDHC!\n");
return -EINVAL;
}
port = (val >> 11) & 0x3;
printf("port %d\n", port);
switch (port) {
case 3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
break;
}
imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
return fsl_esdhc_initialize(bis, &usdhc_cfg);
}

12
board/somlabs/visionsom-6ull/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_SOMLABS_VISIONSOM_6ULL
config SYS_BOARD
default "visionsom-6ull"
config SYS_VENDOR
default "somlabs"
config SYS_CONFIG_NAME
default "somlabs_visionsom_6ull"
endif

6
board/somlabs/visionsom-6ull/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
VISIONSOM-6ULL BOARD
M: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
S: Maintained
F: board/somlabs/visionsom-6ull/
F: include/configs/somlabs_visionsom_6ull.h
F: configs/somlabs_visionsom_6ull_defconfig

4
board/somlabs/visionsom-6ull/Makefile Normal file
View File

@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas@somlabs.com>
obj-y := visionsom-6ull.o

107
board/somlabs/visionsom-6ull/imximage.cfg Normal file
View File

@ -0,0 +1,107 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 A. Karas
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : sd
*/
BOOT_FROM sd
/*
* Secure boot support
*/
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Micron MT41K256M16TW-107 */
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020E04B4 0x000C0000
DATA 4 0x020E04AC 0x00000000
DATA 4 0x020E027C 0x00000030
DATA 4 0x020E0250 0x00000030
DATA 4 0x020E024C 0x00000030
DATA 4 0x020E0490 0x00000030
DATA 4 0x020E0288 0x00000030
DATA 4 0x020E0270 0x00000000
DATA 4 0x020E0260 0x00000030
DATA 4 0x020E0264 0x00000030
DATA 4 0x020E04A0 0x00000030
DATA 4 0x020E0494 0x00020000
DATA 4 0x020E0280 0x00000030
DATA 4 0x020E0284 0x00000030
DATA 4 0x020E04B0 0x00020000
DATA 4 0x020E0498 0x00000030
DATA 4 0x020E04A4 0x00000030
DATA 4 0x020E0244 0x00000030
DATA 4 0x020E0248 0x00000030
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B080C 0x00000000
DATA 4 0x021B083C 0x41570155
DATA 4 0x021B0848 0x4040474A
DATA 4 0x021B0850 0x40405550
DATA 4 0x021B081C 0x33333333
DATA 4 0x021B0820 0x33333333
DATA 4 0x021B082C 0xf3333333
DATA 4 0x021B0830 0xf3333333
DATA 4 0x021B08C0 0x00921012
DATA 4 0x021B08b8 0x00000800
DATA 4 0x021B0004 0x0002002D
DATA 4 0x021B0008 0x1B333030
DATA 4 0x021B000C 0x676B52F3
DATA 4 0x021B0010 0xB66D0B63
DATA 4 0x021B0014 0x01FF00DB
DATA 4 0x021B0018 0x00201740
DATA 4 0x021B001C 0x00008000
DATA 4 0x021B002C 0x000026D2
DATA 4 0x021B0030 0x006B1023
DATA 4 0x021B0040 0x0000004F
DATA 4 0x021B0000 0x84180000
DATA 4 0x021B0890 0x23400A38
DATA 4 0x021B001C 0x02008032
DATA 4 0x021B001C 0x00008033
DATA 4 0x021B001C 0x00048031
DATA 4 0x021B001C 0x15208030
DATA 4 0x021B001C 0x04008040
DATA 4 0x021B0020 0x00000800
DATA 4 0x021B0818 0x00000227
DATA 4 0x021B0004 0x0002552D
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000

146
board/somlabs/visionsom-6ull/visionsom-6ull.c Normal file
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@ -0,0 +1,146 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017-2019 A. Karas, SomLabs
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
*/
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <miiphy.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int mmc_map_to_kernel_blk(int devno)
{
return devno;
}
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
if (is_cpu_type(MXC_CPU_MX6ULL))
env_set("board", "visionsom-6ull");
else
env_set("board", "visionsom-6ul");
return 0;
}
int checkboard(void)
{
printf("Board: SoMLabs VisionSOM-6UL%s\n",
is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
return 0;
}

5
board/toradex/apalis-imx8/apalis-imx8.c
View File

@ -90,11 +90,6 @@ int board_init(void)
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/

5
board/toradex/colibri-imx8x/colibri-imx8x.c
View File

@ -102,11 +102,6 @@ int board_init(void)
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/

1
configs/mx7ulp_evk_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_GPIO=y

1
configs/mx7ulp_evk_plugin_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_NET is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_GPIO=y

49
configs/somlabs_visionsom_6ull_defconfig Normal file
View File

@ -0,0 +1,49 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LZO=y
# CONFIG_EFI_LOADER is not set

9
configs/vining_2000_defconfig
View File

@ -26,6 +26,9 @@ CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@ -74,5 +77,11 @@ CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Softing"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

7
include/configs/mx7ulp_evk.h
View File

@ -14,13 +14,6 @@
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#define SRC_BASE_ADDR CMC1_RBASE
#define IRAM_BASE_ADDR OCRAM_0_BASE
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */

116
include/configs/somlabs_visionsom_6ull.h Normal file
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@ -0,0 +1,116 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017-2019 A. Karas, SomLabs
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
*
* Configuration settings for the SoMlabs VisionSOM 6ULL board.
*/
#ifndef __SOMLABS_VISIONSOM_6ULL_H
#define __SOMLABS_VISIONSOM_6ULL_H
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
#include <asm/mach-imx/gpio.h>
/* SPL options */
#include "imx6_spl.h"
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 1
#endif /* CONFIG_FSL_USDHC */
#define CONFIG_CMD_READ
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"console=ttymxc0\0" \
"initrd_addr=0x86800000\0" \
"fdt_addr=0x83000000\0" \
"script=boot.scr\0" \
"image=zImage\0" \
"splashimage=0x80000000\0" \
"splashfile=/boot/splash.bmp\0" \
"mmcdev=1\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk1p1 rootwait rw\0" \
"setrootmmc=setenv rootspec root=${mmcroot}\0" \
"setbootscriptmmc=setenv loadbootscript " \
"load mmc ${mmcdev}:${mmcpart} " \
"${loadaddr} /boot/${script};\0" \
"setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \
"${loadaddr} /boot/${image}; " \
"setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \
"${fdt_addr} /boot/${fdt_file};\0" \
"setbootargs=setenv bootargs console=${console},${baudrate} " \
"${rootspec}\0" \
"execbootscript=echo Running bootscript...; source\0" \
"setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \
"checkbootdev=run setbootscriptmmc; " \
"run setrootmmc; " \
"run setloadmmc; " \
#define CONFIG_BOOTCOMMAND \
"run setfdtfile; " \
"run checkbootdev; " \
"run loadfdt;" \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run setbootargs; " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"fi; " \
"fi"
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* environment organization */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "eth0"
#endif
#define CONFIG_IMX_THERMAL
#endif

2
include/configs/vining_2000.h
View File

@ -66,12 +66,10 @@
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW

2
include/fsl_validate.h
View File

@ -212,7 +212,7 @@ struct fsl_secboot_sg_table {
/* ESBC global structure.
* Data to be used across verification of different images.
* Stores follwoing Data:
* Stores following Data:
* IE Table
*/
struct fsl_secboot_glb {

2
include/imximage.h
View File

@ -73,7 +73,7 @@ enum imximage_cmd {
CMD_CHECK_BITS_CLR,
CMD_CSF,
CMD_PLUGIN,
/* Follwoing on i.MX8MQ/MM */
/* Following on i.MX8MQ/MM */
CMD_FIT,
CMD_SIGNED_HDMI,
CMD_LOADER,

1
include/spl.h
View File

@ -269,6 +269,7 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
void spl_board_prepare_for_linux(void);
void spl_board_prepare_for_boot(void);
int spl_board_ubi_load_image(u32 boot_device);
int spl_board_boot_device(u32 boot_device);
/**
* jump_to_image_linux() - Jump to a Linux kernel from SPL