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![]() Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> |
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.. | ||
cache-l2x0.c | ||
cache-uclass.c | ||
cache-v5l2.c | ||
Kconfig | ||
Makefile | ||
sandbox_cache.c |