mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-23 10:28:51 +09:00
![Wolfgang Grandegger](/assets/img/avatar_default.png)
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK and MCVEVP baseboard. The board can boot
from eMMC. Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d5
("board/aries: Remove"). I will now take care of them.
The device-tree files are from mainline Linux commit e93c9c99a629
("Linux v5.1)".
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
CC: Marek Vasut <marex@denx.de>
CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
219 lines
4.3 KiB
C
219 lines
4.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
|
|
/*
|
|
* Altera SoCFPGA PinMux configuration
|
|
*/
|
|
|
|
#ifndef __SOCFPGA_PINMUX_CONFIG_H__
|
|
#define __SOCFPGA_PINMUX_CONFIG_H__
|
|
|
|
const u8 sys_mgr_init_table[] = {
|
|
3, /* EMACIO0 */
|
|
3, /* EMACIO1 */
|
|
3, /* EMACIO2 */
|
|
3, /* EMACIO3 */
|
|
3, /* EMACIO4 */
|
|
3, /* EMACIO5 */
|
|
3, /* EMACIO6 */
|
|
3, /* EMACIO7 */
|
|
3, /* EMACIO8 */
|
|
3, /* EMACIO9 */
|
|
3, /* EMACIO10 */
|
|
3, /* EMACIO11 */
|
|
3, /* EMACIO12 */
|
|
3, /* EMACIO13 */
|
|
0, /* EMACIO14 */
|
|
0, /* EMACIO15 */
|
|
0, /* EMACIO16 */
|
|
0, /* EMACIO17 */
|
|
0, /* EMACIO18 */
|
|
0, /* EMACIO19 */
|
|
3, /* FLASHIO0 */
|
|
0, /* FLASHIO1 */
|
|
3, /* FLASHIO2 */
|
|
3, /* FLASHIO3 */
|
|
3, /* FLASHIO4 */
|
|
3, /* FLASHIO5 */
|
|
3, /* FLASHIO6 */
|
|
3, /* FLASHIO7 */
|
|
0, /* FLASHIO8 */
|
|
3, /* FLASHIO9 */
|
|
3, /* FLASHIO10 */
|
|
3, /* FLASHIO11 */
|
|
0, /* GENERALIO0 */
|
|
1, /* GENERALIO1 */
|
|
1, /* GENERALIO2 */
|
|
0, /* GENERALIO3 */
|
|
0, /* GENERALIO4 */
|
|
1, /* GENERALIO5 */
|
|
1, /* GENERALIO6 */
|
|
1, /* GENERALIO7 */
|
|
1, /* GENERALIO8 */
|
|
0, /* GENERALIO9 */
|
|
0, /* GENERALIO10 */
|
|
0, /* GENERALIO11 */
|
|
0, /* GENERALIO12 */
|
|
2, /* GENERALIO13 */
|
|
2, /* GENERALIO14 */
|
|
1, /* GENERALIO15 */
|
|
1, /* GENERALIO16 */
|
|
1, /* GENERALIO17 */
|
|
1, /* GENERALIO18 */
|
|
0, /* GENERALIO19 */
|
|
0, /* GENERALIO20 */
|
|
0, /* GENERALIO21 */
|
|
0, /* GENERALIO22 */
|
|
0, /* GENERALIO23 */
|
|
0, /* GENERALIO24 */
|
|
0, /* GENERALIO25 */
|
|
0, /* GENERALIO26 */
|
|
0, /* GENERALIO27 */
|
|
0, /* GENERALIO28 */
|
|
0, /* GENERALIO29 */
|
|
0, /* GENERALIO30 */
|
|
0, /* GENERALIO31 */
|
|
0, /* MIXED1IO0 */
|
|
1, /* MIXED1IO1 */
|
|
1, /* MIXED1IO2 */
|
|
1, /* MIXED1IO3 */
|
|
1, /* MIXED1IO4 */
|
|
0, /* MIXED1IO5 */
|
|
0, /* MIXED1IO6 */
|
|
0, /* MIXED1IO7 */
|
|
1, /* MIXED1IO8 */
|
|
1, /* MIXED1IO9 */
|
|
1, /* MIXED1IO10 */
|
|
1, /* MIXED1IO11 */
|
|
0, /* MIXED1IO12 */
|
|
0, /* MIXED1IO13 */
|
|
0, /* MIXED1IO14 */
|
|
1, /* MIXED1IO15 */
|
|
1, /* MIXED1IO16 */
|
|
1, /* MIXED1IO17 */
|
|
1, /* MIXED1IO18 */
|
|
0, /* MIXED1IO19 */
|
|
0, /* MIXED1IO20 */
|
|
0, /* MIXED1IO21 */
|
|
0, /* MIXED2IO0 */
|
|
0, /* MIXED2IO1 */
|
|
0, /* MIXED2IO2 */
|
|
0, /* MIXED2IO3 */
|
|
0, /* MIXED2IO4 */
|
|
0, /* MIXED2IO5 */
|
|
0, /* MIXED2IO6 */
|
|
0, /* MIXED2IO7 */
|
|
0, /* GPLINMUX48 */
|
|
0, /* GPLINMUX49 */
|
|
0, /* GPLINMUX50 */
|
|
0, /* GPLINMUX51 */
|
|
0, /* GPLINMUX52 */
|
|
0, /* GPLINMUX53 */
|
|
0, /* GPLINMUX54 */
|
|
0, /* GPLINMUX55 */
|
|
0, /* GPLINMUX56 */
|
|
0, /* GPLINMUX57 */
|
|
0, /* GPLINMUX58 */
|
|
0, /* GPLINMUX59 */
|
|
0, /* GPLINMUX60 */
|
|
0, /* GPLINMUX61 */
|
|
0, /* GPLINMUX62 */
|
|
0, /* GPLINMUX63 */
|
|
0, /* GPLINMUX64 */
|
|
0, /* GPLINMUX65 */
|
|
0, /* GPLINMUX66 */
|
|
0, /* GPLINMUX67 */
|
|
0, /* GPLINMUX68 */
|
|
0, /* GPLINMUX69 */
|
|
0, /* GPLINMUX70 */
|
|
1, /* GPLMUX0 */
|
|
1, /* GPLMUX1 */
|
|
1, /* GPLMUX2 */
|
|
1, /* GPLMUX3 */
|
|
1, /* GPLMUX4 */
|
|
1, /* GPLMUX5 */
|
|
1, /* GPLMUX6 */
|
|
1, /* GPLMUX7 */
|
|
1, /* GPLMUX8 */
|
|
1, /* GPLMUX9 */
|
|
1, /* GPLMUX10 */
|
|
1, /* GPLMUX11 */
|
|
1, /* GPLMUX12 */
|
|
1, /* GPLMUX13 */
|
|
1, /* GPLMUX14 */
|
|
1, /* GPLMUX15 */
|
|
1, /* GPLMUX16 */
|
|
1, /* GPLMUX17 */
|
|
1, /* GPLMUX18 */
|
|
1, /* GPLMUX19 */
|
|
1, /* GPLMUX20 */
|
|
1, /* GPLMUX21 */
|
|
1, /* GPLMUX22 */
|
|
1, /* GPLMUX23 */
|
|
1, /* GPLMUX24 */
|
|
1, /* GPLMUX25 */
|
|
1, /* GPLMUX26 */
|
|
1, /* GPLMUX27 */
|
|
1, /* GPLMUX28 */
|
|
1, /* GPLMUX29 */
|
|
1, /* GPLMUX30 */
|
|
1, /* GPLMUX31 */
|
|
1, /* GPLMUX32 */
|
|
1, /* GPLMUX33 */
|
|
1, /* GPLMUX34 */
|
|
1, /* GPLMUX35 */
|
|
1, /* GPLMUX36 */
|
|
1, /* GPLMUX37 */
|
|
1, /* GPLMUX38 */
|
|
1, /* GPLMUX39 */
|
|
1, /* GPLMUX40 */
|
|
1, /* GPLMUX41 */
|
|
1, /* GPLMUX42 */
|
|
1, /* GPLMUX43 */
|
|
1, /* GPLMUX44 */
|
|
1, /* GPLMUX45 */
|
|
1, /* GPLMUX46 */
|
|
1, /* GPLMUX47 */
|
|
1, /* GPLMUX48 */
|
|
1, /* GPLMUX49 */
|
|
1, /* GPLMUX50 */
|
|
1, /* GPLMUX51 */
|
|
1, /* GPLMUX52 */
|
|
1, /* GPLMUX53 */
|
|
1, /* GPLMUX54 */
|
|
1, /* GPLMUX55 */
|
|
1, /* GPLMUX56 */
|
|
1, /* GPLMUX57 */
|
|
1, /* GPLMUX58 */
|
|
1, /* GPLMUX59 */
|
|
1, /* GPLMUX60 */
|
|
1, /* GPLMUX61 */
|
|
1, /* GPLMUX62 */
|
|
1, /* GPLMUX63 */
|
|
1, /* GPLMUX64 */
|
|
1, /* GPLMUX65 */
|
|
1, /* GPLMUX66 */
|
|
1, /* GPLMUX67 */
|
|
1, /* GPLMUX68 */
|
|
1, /* GPLMUX69 */
|
|
1, /* GPLMUX70 */
|
|
0, /* NANDUSEFPGA */
|
|
0, /* UART0USEFPGA */
|
|
0, /* RGMII1USEFPGA */
|
|
0, /* SPIS0USEFPGA */
|
|
0, /* CAN0USEFPGA */
|
|
0, /* I2C0USEFPGA */
|
|
0, /* SDMMCUSEFPGA */
|
|
0, /* QSPIUSEFPGA */
|
|
0, /* SPIS1USEFPGA */
|
|
0, /* RGMII0USEFPGA */
|
|
1, /* UART1USEFPGA */
|
|
0, /* CAN1USEFPGA */
|
|
0, /* USB1USEFPGA */
|
|
0, /* I2C3USEFPGA */
|
|
0, /* I2C2USEFPGA */
|
|
0, /* I2C1USEFPGA */
|
|
0, /* SPIM1USEFPGA */
|
|
0, /* USB0USEFPGA */
|
|
0 /* SPIM0USEFPGA */
|
|
};
|
|
#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
|