mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
![Michael Krummsdorf](/assets/img/avatar_default.png)
The device trees for TQMa6x SOM support variations in - CPU type: imx6dl- or imx6q- - MBa6 I2C bus access: -mba6a (i2c1) or -mba6b (i2c3) (plus the respective common/module include trees) - USBH1 is directly connected to a hub - USBOTG is connected to a separate connector and can act as host/device or full OTG port. Signed-off-by: Michael Krummsdorf <michael.krummsdorf@ew.tq-group.com>
208 lines
5.3 KiB
Plaintext
208 lines
5.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (C) 2020 TQ-Systems GmbH
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/ {
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aliases {
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mmc1 = &usdhc2;
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};
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chosen {
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linux,stdout-path = &uart2;
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stdout-path = &uart2;
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};
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regulators {
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reg_mba6_3p3v: regulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "supply-mba6-3p3v";
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reg = <1>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_otgvbus: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_otgpwr>;
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regulator-name = "otg-vbus-supply";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin_supply = <®_3p3v>;
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};
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};
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};
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&fec {
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <100>;
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phy-handle = <ðphy>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@3 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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reg = <3>;
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force-master;
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max-speed = <1000>;
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interrupt-parent = <&gpio1>;
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interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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mba6 {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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/* FEC phy IRQ */
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MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008
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/* FEC phy reset */
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099
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/* DSE = 100, 100k up, SPEED = MED */
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0
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/* DSE = 111, pull 100k up */
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
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/* DSE = 111, pull external */
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
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/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */
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MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */
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/* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099
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MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
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MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099
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MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
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MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
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MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
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MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
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MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
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MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
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MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099
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MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
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MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
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MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
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MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
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MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099
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MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
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MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
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MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
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MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099
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MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
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MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
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MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
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MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
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MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
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>;
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};
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pinctrl_reg_otgpwr: regotgpwrgrp {
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fsl,pins = <
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/* OTG_PWR */
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MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
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MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071
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/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059
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MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
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MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
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MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
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MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */
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MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */
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>;
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};
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pinctrl_usbotg: usbotggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
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MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059
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>;
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};
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbh1 {
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disable-over-current;
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status = "okay";
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};
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&usbotg {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg>;
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dr_mode = "otg";
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vbus-supply = <®_otgvbus>;
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status = "okay";
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};
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&usdhc2 { /* Baseboard Slot */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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vmmc-supply = <®_mba6_3p3v>;
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bus-width = <4>;
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no-1-8-v;
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cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&wdog1 {
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status = "okay";
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};
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