u-boot-brain/arch/arm/cpu/armv8
Peng Fan 208bd51396 arm: armv8 correct value passed to __asm_dcache_all
>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"

Current value 0xffff can make invalidate work, since we only judge whether
input value is 0 or not, see following code:
"
    tbz     w1, #0, 1f
    dc      isw, x9
    b       2f
1:  dc      cisw, x9      /* clean & invalidate by set/way */
2:  subs    x6, x6, #1    /* decrement the way */
"

Later we may add "2 clean only" support. So following the comments,
correct value from 0xffff to 1.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2015-09-12 09:03:39 +02:00
..
fsl-lsch3 armv8: fsl-lsch3: Rewrite MMU translation table entries 2015-09-01 21:49:27 -05:00
hisilicon hisilicon: hi6220: Add a hi6220 pinmux driver. 2015-08-12 20:48:00 -04:00
zynqmp zynqmp: usb: Add usb dwc3 driver support for zynqmp 2015-08-19 11:27:30 +02:00
cache_v8.c armv8: fsl-lsch3: Rewrite MMU translation table entries 2015-09-01 21:49:27 -05:00
cache.S arm: armv8 correct value passed to __asm_dcache_all 2015-09-12 09:03:39 +02:00
config.mk ARM: move -march=* and -mtune= options to arch/arm/Makefile 2015-03-27 16:55:22 +01:00
cpu.c arm64: core support 2014-01-09 16:08:44 +01:00
exceptions.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
generic_timer.c armv8/fsl-lsch3: Implement workaround for erratum A008585 2015-04-23 08:55:54 -07:00
Kconfig armv8/vexpress64: make multientry conditional 2015-03-09 11:13:29 -04:00
Makefile hisilicon: hi6220: Add a hi6220 pinmux driver. 2015-08-12 20:48:00 -04:00
start.S arm/errata: Update required bits for A57 cores erratas 2015-07-20 11:44:35 -07:00
tlb.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
transition.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
u-boot-spl.lds armv8/ls2085aqds: NAND boot support 2015-04-23 16:46:50 -07:00
u-boot.lds arm64: core support 2014-01-09 16:08:44 +01:00