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![Hans de Goede](/assets/img/avatar_default.png)
Our old hardcoded k and m values are based on PLL5 being configured in steps of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i) the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps. This commit adjusts clock_set_pll5 to automatically select the best k and m depending on the requested clk rate. Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
193 lines
4.9 KiB
C
193 lines
4.9 KiB
C
/*
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* sun6i specific clock code
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_SPL_BUILD
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void clock_init_safe(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_prcm_reg * const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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/* Set PLL ldo voltage without this PLL6 does not work properly */
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clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
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PRCM_PLL_CTRL_LDO_KEY);
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clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
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PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
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PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
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clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
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clock_set_pll1(408000000);
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writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
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writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
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writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
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writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
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}
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#endif
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void clock_init_uart(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#if CONFIG_CONS_INDEX < 5
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/* uart clock source is apb2 */
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writel(APB2_CLK_SRC_OSC24M|
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APB2_CLK_RATE_N_1|
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APB2_CLK_RATE_M(1),
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&ccm->apb2_div);
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/* open the clock for uart */
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->apb2_reset_cfg,
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1 << (APB2_RESET_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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#else
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/* enable R_PIO and R_UART clocks, and de-assert resets */
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prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
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#endif
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/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
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writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
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}
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int clock_twi_onoff(int port, int state)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (port > 3)
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return -1;
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/* set the apb clock gate for twi */
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if (state)
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
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else
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clrbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void clock_set_pll1(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int k = 1;
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int m = 1;
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if (clk > 1152000000) {
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k = 2;
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} else if (clk > 768000000) {
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k = 3;
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m = 2;
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}
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/* Switch to 24MHz clock while changing PLL1 */
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writel(AXI_DIV_3 << AXI_DIV_SHIFT |
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ATB_DIV_2 << ATB_DIV_SHIFT |
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CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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/* PLL1 rate = 24000000 * n * k / m */
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
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CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
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CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
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sdelay(200);
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/* Switch CPU to PLL1 */
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writel(AXI_DIV_3 << AXI_DIV_SHIFT |
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ATB_DIV_2 << ATB_DIV_SHIFT |
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CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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}
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#endif
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void clock_set_pll3(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
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if (clk == 0) {
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clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
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return;
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}
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/* PLL3 rate = 24000000 * n / m */
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writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
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CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
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&ccm->pll3_cfg);
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}
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void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int max_n = 32;
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int k = 1, m = 2;
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if (sigma_delta_enable)
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writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
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/* PLL5 rate = 24000000 * n * k / m */
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if (clk > 24000000 * k * max_n / m) {
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m = 1;
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if (clk > 24000000 * k * max_n / m)
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k = 2;
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}
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writel(CCM_PLL5_CTRL_EN |
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(sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
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CCM_PLL5_CTRL_UPD |
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CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
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CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
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udelay(5500);
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}
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unsigned int clock_get_pll6(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->pll6_cfg);
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int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
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int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
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return 24000000 * n * k / 2;
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}
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void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
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{
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int pll = clock_get_pll6() * 2;
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int div = 1;
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while ((pll / div) > hz)
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div++;
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writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
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clk_cfg);
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}
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