mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
8f74e659c4
Due to how the Makefile logic is we currently get DM_SPI support in SPL enabled by having DM_SPI enabled for full U-Boot but not having CONFIG_SPL_DM_SPI set. Add this missing option to boards that were inadvertently making use of it. Cc: Adam Ford <aford173@gmail.com> Cc: Akash Gajjar <akash@openedev.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Andy Yan <andy.yan@rock-chips.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Chee Hong Ang <chee.hong.ang@intel.com> Cc: Chin-Liang See <clsee@altera.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Cc: Levin Du <djw@t-chip.com.cn> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Luca Ceresoli <luca@lucaceresoli.net> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Pavel Machek <pavel@denx.de> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Suniel Mahesh <sunil@amarulasolutions.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
81 lines
2.0 KiB
Plaintext
81 lines
2.0 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_ENV_SIZE=0x6000
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CONFIG_ENV_OFFSET=0x460000
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CONFIG_ENV_SECT_SIZE=0x1000
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CONFIG_SPL_DM_SPI=y
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CONFIG_ROCKCHIP_RK3399=y
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CONFIG_TARGET_ROC_PC_RK3399=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DEBUG_UART_BASE=0xFF1A0000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI_SUPPORT=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_TPL=y
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CONFIG_TPL_GPIO_SUPPORT=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIME=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_NVME=y
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CONFIG_PCI=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM_RK3399_LPDDR4=y
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CONFIG_DM_RESET=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_ROCKCHIP_SPI=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_DM_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_DISPLAY_ROCKCHIP_HDMI=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_ERRNO_STR=y
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