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https://github.com/brain-hackers/u-boot-brain
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7357c2cbc0
The SPL for socfpga gen5 currently takes all peripherals out of reset unconditionally. To implement proper reset handling for peripherals, the reset node has to be provided with the SPL dts. In preparation to move the DDR driver to DM, the sdr node is required in SPL, too. This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon files so that the reset manager and SDR driver correctly probe in SPL. It centralizes these settings into a common file since in contrast to boot-type specific nodes, "soc", "rst" and "sdr" are always needed. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
71 lines
938 B
Plaintext
71 lines
938 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* Copyright (c) 2018 Simon Goldschmidt
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*/
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#include "socfpga-common-u-boot.dtsi"
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/{
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aliases {
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spi0 = "/soc/spi@ff705000";
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udc0 = &usb1;
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};
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};
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&can0 {
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status = "okay";
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};
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&watchdog0 {
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status = "disabled";
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};
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&mmc {
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u-boot,dm-pre-reloc;
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};
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&qspi {
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u-boot,dm-pre-reloc;
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};
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&flash0 {
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compatible = "n25q00", "jedec,spi-nor";
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u-boot,dm-pre-reloc;
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partition@qspi-boot {
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/* 8MB for raw data. */
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label = "Flash 0 Raw Data";
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reg = <0x0 0x800000>;
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};
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partition@qspi-rootfs {
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/* 120MB for jffs2 data. */
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label = "Flash 0 jffs2 Filesystem";
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reg = <0x800000 0x7800000>;
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};
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};
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&uart0 {
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clock-frequency = <100000000>;
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u-boot,dm-pre-reloc;
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};
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&uart1 {
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clock-frequency = <100000000>;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&portc {
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bank-name = "portc";
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};
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