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arm: socfpga: gen5: add reset & sdr node to SPL devicetrees

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The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
the reset node has to be provided with the SPL dts.

In preparation to move the DDR driver to DM, the sdr node is required
in SPL, too.

This patch adds "u-boot,dm-pre-reloc" to U-Boot specific dtsi addon
files so that the reset manager and SDR driver correctly probe in SPL.
It centralizes these settings into a common file since in contrast to
boot-type specific nodes, "soc", "rst" and "sdr" are always needed.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Simon Goldschmidt 2019-03-01 20:12:29 +01:00 committed by Marek Vasut
parent 42a37d9774
commit 7357c2cbc0
12 changed files with 36 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/dts/socfpga-common-u-boot.dtsi Normal file
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@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* Copyright (c) 2019 Simon Goldschmidt
*/
/{
soc {
u-boot,dm-pre-reloc;
};
};
&rst {
u-boot,dm-pre-reloc;
};
&sdr {
u-boot,dm-pre-reloc;
};

6
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
View File

@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
soc {
u-boot,dm-pre-reloc;
};
};
&watchdog0 {

5
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
View File

@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "Devboards.de DBM-SoC1";
@ -24,10 +25,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
soc {
u-boot,dm-pre-reloc;
};
};
&gmac1 {

6
arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
View File

@ -6,14 +6,12 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
udc0 = &usb1;
};
soc {
u-boot,dm-pre-reloc;
};
};
&watchdog0 {

5
arch/arm/dts/socfpga_cyclone5_de10_nano.dts
View File

@ -6,6 +6,7 @@
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "Terasic DE10-Nano";
@ -26,10 +27,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
soc {
u-boot,dm-pre-reloc;
};
};
&gmac1 {

5
arch/arm/dts/socfpga_cyclone5_de1_soc.dts
View File

@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "Terasic DE1-SoC";
@ -24,10 +25,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
soc {
u-boot,dm-pre-reloc;
};
};
&gmac1 {

5
arch/arm/dts/socfpga_cyclone5_is1.dts
View File

@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V IS1";
@ -31,10 +32,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
soc {
u-boot,dm-pre-reloc;
};
};
&gmac1 {

6
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
View File

@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
soc {
u-boot,dm-pre-reloc;
};
};
&can0 {

6
arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
View File

@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
soc {
u-boot,dm-pre-reloc;
};
};
&watchdog0 {

6
arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
View File

@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
soc {
u-boot,dm-pre-reloc;
};
};
&watchdog0 {

5
arch/arm/dts/socfpga_cyclone5_sr1500.dts
View File

@ -4,6 +4,7 @@
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "SoCFPGA Cyclone V SR1500";
@ -27,10 +28,6 @@
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
soc {
u-boot,dm-pre-reloc;
};
};
&gmac1 {

6
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
View File

@ -6,15 +6,13 @@
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb0;
};
soc {
u-boot,dm-pre-reloc;
};
};
&watchdog0 {