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https://github.com/brain-hackers/u-boot-brain
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25a1b5efb3
This patch add pwm support for mt7622, mt7623 and mt7629 SoCs Signed-off-by: Sam Shih <sam.shih@mediatek.com>
250 lines
6.3 KiB
Plaintext
250 lines
6.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <dt-bindings/power/mt7629-power.h>
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#include <dt-bindings/reset/mt7629-reset.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7622";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clock-frequency = <1300000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clock-frequency = <1300000000>;
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};
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};
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snfi: snfi@1100d000 {
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compatible = "mediatek,mtk-snfi-spi";
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reg = <0x1100d000 0x2000>;
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clocks = <&pericfg CLK_PERI_NFI_PD>,
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<&pericfg CLK_PERI_SNFI_PD>;
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clock-names = "nfi_clk", "pad_clk";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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<&topckgen CLK_TOP_NFI_INFRA_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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<&topckgen CLK_TOP_UNIVPLL2_D8>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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arm,cpu-registers-not-fw-configured;
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};
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timer0: timer@10004000 {
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>;
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clock-names = "system-clk";
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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infracfg: infracfg@10000000 {
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compatible = "mediatek,mt7622-infracfg",
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"syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: pericfg@10002000 {
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compatible = "mediatek,mt7622-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7622-scpsys",
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"syscon";
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#power-domain-cells = <1>;
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reg = <0x10006000 0x1000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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};
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,sysirq";
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reg = <0x10200620 0x20>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt7622-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@10210000 {
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compatible = "mediatek,mt7622-topckgen";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@10211000 {
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compatible = "mediatek,mt7622-pinctrl";
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reg = <0x10211000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,wdt";
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reg = <0x10212000 0x800>;
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART0_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7622-mmc";
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reg = <0x11230000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
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<&topckgen CLK_TOP_MSDC50_0_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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mmc1: mmc@11240000 {
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compatible = "mediatek,mt7622-mmc";
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reg = <0x11240000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
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<&topckgen CLK_TOP_AXI_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7622-ethsys", "syscon";
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reg = <0x1b000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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eth: ethernet@1b100000 {
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compatible = "mediatek,mt7622-eth", "syscon";
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reg = <0x1b100000 0x20000>;
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clocks = <&topckgen CLK_TOP_ETH_SEL>,
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<ðsys CLK_ETH_ESW_EN>,
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<ðsys CLK_ETH_GP0_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<&sgmiisys CLK_SGMII_TX250M_EN>,
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<&sgmiisys CLK_SGMII_RX250M_EN>,
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<&sgmiisys CLK_SGMII_CDR_REF>,
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<&sgmiisys CLK_SGMII_CDR_FB>,
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<&topckgen CLK_TOP_SGMIIPLL>,
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<&apmixedsys CLK_APMIXED_ETH2PLL>;
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clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
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"sgmii_tx250m", "sgmii_rx250m",
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"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
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"eth2pll";
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power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
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resets = <ðsys ETHSYS_FE_RST>;
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reset-names = "fe";
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sgmiisys: sgmiisys@1b128000 {
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compatible = "mediatek,mt7622-sgmiisys", "syscon";
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reg = <0x1b128000 0x3000>;
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#clock-cells = <1>;
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};
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pwm: pwm@11006000 {
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compatible = "mediatek,mt7622-pwm";
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reg = <0x11006000 0x1000>;
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#clock-cells = <1>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM_PD>,
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<&pericfg CLK_PERI_PWM1_PD>,
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<&pericfg CLK_PERI_PWM2_PD>,
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<&pericfg CLK_PERI_PWM3_PD>,
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<&pericfg CLK_PERI_PWM4_PD>,
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<&pericfg CLK_PERI_PWM5_PD>,
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<&pericfg CLK_PERI_PWM6_PD>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
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"pwm5", "pwm6";
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status = "disabled";
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};
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};
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