mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ccc7595a81
as we switch to support DM and DTS, rework the existing DTS trees. Change also Linux specific Device trees, goal is to push this changes to linux. Collect U-Boot specific changes in separate "*u-boot*" dts files. Signed-off-by: Heiko Schocher <hs@denx.de>
245 lines
5.9 KiB
Plaintext
245 lines
5.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2 board
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
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*
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include "imx6qdl-aristainetos2-common.dtsi"
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/ {
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio>;
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LED_blue {
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label = "led_blue";
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gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
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};
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LED_green {
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label = "led_green";
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gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
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};
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LED_red {
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label = "led_red";
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gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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};
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LED_yellow {
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label = "led_yellow";
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gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
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};
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LED_ena {
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label = "led_ena";
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gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&ecspi1 {
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fsl,spi-num-chipselects = <3>;
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cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
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&gpio4 10 GPIO_ACTIVE_HIGH
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&gpio4 11 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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};
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&ecspi4 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi4>;
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status = "okay";
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pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
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flash: m25p80@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <1>;
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};
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};
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&gpio7 {
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sd2_driver_ena {
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gpio-hog;
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output-high;
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gpios = <8 GPIO_ACTIVE_HIGH>;
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
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MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
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MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
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>;
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};
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pinctrl_ecspi4: ecspi4grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
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MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
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MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
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MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
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MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */
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>;
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};
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pinctrl_gpio: gpiogrp {
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fsl,pins = <
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/* led enable */
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
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/* LCD power enable */
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
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/* led yellow */
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MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
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/* led red */
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MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
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/* led green */
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MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
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/* led blue */
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MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
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/* Profibus IRQ */
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MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
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/* FPGA IRQ currently unused*/
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MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
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/* Display reset because of clock failure */
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MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
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/* spi bus #2 SS driver enable */
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MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
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/* RST_LOC# PHY reset input (has pull-down!)*/
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
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/* USB_OTG_ID = GPIO1_24*/
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MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0
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/* Touchscreen IRQ */
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MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
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/* PCIe reset */
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MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
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>;
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};
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pinctrl_gpmi_nand: gpmi-nand {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
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MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
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MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
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>;
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};
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pinctrl_usbotg: usbotggrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
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MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
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MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
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MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
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MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
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MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
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/* SD1 card detect input */
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
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/* SD1 write protect input */
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
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MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
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MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
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MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
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MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
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/* SD2 level shifter output enable */
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MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
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/* SD2 card detect input */
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MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
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/* SD2 write protect input */
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MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
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>;
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};
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};
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