mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-22 04:30:31 +09:00
16bb08d19a
A Tegra114 HW bug prevents the main CPU vector from being modified under certain circumstances. Tegra114 A01P and later with a patched boot ROM set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing an arbitrary jump instruction at that location, in order to redirect to the desired reset vector location. Modify Tegra114's start_cpu() to make use of this feature. This allows CPUs with the patched boot ROM to boot. Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
327 lines
9.5 KiB
C
327 lines
9.5 KiB
C
/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include "../tegra-common/cpu.h"
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/* Tegra114-specific CPU init code */
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static void enable_cpu_power_rail(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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debug("enable_cpu_power_rail entry\n");
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/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
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pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
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pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
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/*
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* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
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* set it for 25ms (102MHz * .025)
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*/
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reg = 0x26E8F0;
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writel(reg, &pmc->pmc_cpupwrgood_timer);
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/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
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clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
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setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
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/*
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* Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
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* to 408 to satisfy the requirement of having at least 16 CPU clock
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* cycles before clamp removal.
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*/
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clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
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setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
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}
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static void enable_cpu_clocks(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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debug("enable_cpu_clocks entry\n");
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/* Wait for PLL-X to lock */
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do {
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reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
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} while ((reg & (1 << 27)) == 0);
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/* Wait until all clocks are stable */
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udelay(PLL_STABILIZATION_DELAY);
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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/* Always enable the main CPU complex clocks */
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clock_enable(PERIPH_ID_CPU);
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clock_enable(PERIPH_ID_CPULP);
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clock_enable(PERIPH_ID_CPUG);
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}
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static void remove_cpu_resets(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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debug("remove_cpu_resets entry\n");
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/* Take the slow non-CPU partition out of reset */
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reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
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writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
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/* Take the fast non-CPU partition out of reset */
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reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
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writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
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/* Clear the SW-controlled reset of the slow cluster */
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reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
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reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
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writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
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/* Clear the SW-controlled reset of the fast cluster */
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reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
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reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
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reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
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reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
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reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
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writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
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}
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/**
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* The T114 requires some special clock initialization, including setting up
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* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
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*/
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void t114_init_clocks(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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u32 val;
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debug("t114_init_clocks entry\n");
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/* Set active CPU cluster to G */
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clrbits_le32(&flow->cluster_control, 1);
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/*
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* Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
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* at 108 MHz. This is glitch free as only the source is changed, no
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* special precaution needed.
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*/
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val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
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(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
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(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
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(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
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(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
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writel(val, &clkrst->crc_sclk_brst_pol);
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writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
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debug("Setting up PLLX\n");
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init_pllx();
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val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
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writel(val, &clkrst->crc_clk_sys_rate);
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/* Enable clocks to required peripherals. TBD - minimize this list */
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debug("Enabling clocks\n");
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clock_set_enable(PERIPH_ID_CACHE2, 1);
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clock_set_enable(PERIPH_ID_GPIO, 1);
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clock_set_enable(PERIPH_ID_TMR, 1);
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clock_set_enable(PERIPH_ID_RTC, 1);
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clock_set_enable(PERIPH_ID_CPU, 1);
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clock_set_enable(PERIPH_ID_EMC, 1);
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clock_set_enable(PERIPH_ID_I2C5, 1);
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clock_set_enable(PERIPH_ID_FUSE, 1);
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clock_set_enable(PERIPH_ID_PMC, 1);
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clock_set_enable(PERIPH_ID_APBDMA, 1);
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clock_set_enable(PERIPH_ID_MEM, 1);
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clock_set_enable(PERIPH_ID_IRAMA, 1);
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clock_set_enable(PERIPH_ID_IRAMB, 1);
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clock_set_enable(PERIPH_ID_IRAMC, 1);
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clock_set_enable(PERIPH_ID_IRAMD, 1);
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clock_set_enable(PERIPH_ID_CORESIGHT, 1);
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clock_set_enable(PERIPH_ID_MSELECT, 1);
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clock_set_enable(PERIPH_ID_EMC1, 1);
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clock_set_enable(PERIPH_ID_MC1, 1);
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clock_set_enable(PERIPH_ID_DVFS, 1);
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/* Switch MSELECT clock to PLLP (00) */
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clock_ll_set_source(PERIPH_ID_MSELECT, 0);
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/*
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* Clock divider request for 102MHz would setup MSELECT clock as
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* 102MHz for PLLP base 408MHz
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*/
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clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
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(NVBL_PLLP_KHZ/102000));
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/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
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clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
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/* Give clocks time to stabilize */
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udelay(1000);
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/* Take required peripherals out of reset */
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debug("Taking periphs out of reset\n");
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reset_set_enable(PERIPH_ID_CACHE2, 0);
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reset_set_enable(PERIPH_ID_GPIO, 0);
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reset_set_enable(PERIPH_ID_TMR, 0);
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reset_set_enable(PERIPH_ID_COP, 0);
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reset_set_enable(PERIPH_ID_EMC, 0);
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reset_set_enable(PERIPH_ID_I2C5, 0);
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reset_set_enable(PERIPH_ID_FUSE, 0);
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reset_set_enable(PERIPH_ID_APBDMA, 0);
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reset_set_enable(PERIPH_ID_MEM, 0);
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reset_set_enable(PERIPH_ID_CORESIGHT, 0);
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reset_set_enable(PERIPH_ID_MSELECT, 0);
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reset_set_enable(PERIPH_ID_EMC1, 0);
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reset_set_enable(PERIPH_ID_MC1, 0);
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reset_set_enable(PERIPH_ID_DVFS, 0);
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debug("t114_init_clocks exit\n");
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}
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static int is_partition_powered(u32 mask)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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/* Get power gate status */
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reg = readl(&pmc->pmc_pwrgate_status);
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return (reg & mask) == mask;
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}
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static int is_clamp_enabled(u32 mask)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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/* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
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reg = readl(&pmc->pmc_pwrgate_timer_on);
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return (reg & mask) == mask;
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}
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static void power_partition(u32 status, u32 partid)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
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/* Is the partition already on? */
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if (!is_partition_powered(status)) {
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/* No, toggle the partition power state (OFF -> ON) */
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debug("power_partition, toggling state\n");
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clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
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setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
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setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
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/* Wait for the power to come up */
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while (!is_partition_powered(status))
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;
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/* Wait for the clamp status to be cleared */
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while (is_clamp_enabled(status))
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;
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/* Give I/O signals time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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}
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}
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void powerup_cpus(void)
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{
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debug("powerup_cpus entry\n");
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/* We boot to the fast cluster */
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debug("powerup_cpus entry: G cluster\n");
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/* Power up the fast cluster rail partition */
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power_partition(CRAIL, CRAILID);
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/* Power up the fast cluster non-CPU partition */
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power_partition(C0NC, C0NCID);
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/* Power up the fast cluster CPU0 partition */
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power_partition(CE0, CE0ID);
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}
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void start_cpu(u32 reset_vector)
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{
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u32 imme, inst;
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debug("start_cpu entry, reset_vector = %x\n", reset_vector);
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t114_init_clocks();
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/* Enable VDD_CPU */
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enable_cpu_power_rail();
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/* Get the CPU(s) running */
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enable_cpu_clocks();
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/* Enable CoreSight */
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clock_enable_coresight(1);
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/* Take CPU(s) out of reset */
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remove_cpu_resets();
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/* Set the entry point for CPU execution from reset */
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/*
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* A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
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* See nvbug 1193357 for details.
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*/
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/* mov r0, #lsb(reset_vector) */
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imme = reset_vector & 0xffff;
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inst = imme & 0xfff;
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inst |= ((imme >> 12) << 16);
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inst |= 0xe3000000;
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writel(inst, 0x4003fff0);
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/* movt r0, #msb(reset_vector) */
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imme = (reset_vector >> 16) & 0xffff;
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inst = imme & 0xfff;
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inst |= ((imme >> 12) << 16);
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inst |= 0xe3400000;
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writel(inst, 0x4003fff4);
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/* bx r0 */
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writel(0xe12fff10, 0x4003fff8);
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/* b -12 */
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imme = (u32)-20;
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inst = (imme >> 2) & 0xffffff;
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inst |= 0xea000000;
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writel(inst, 0x4003fffc);
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/* Write to orignal location for compatibility */
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writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/* If the CPU(s) don't already have power, power 'em up */
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powerup_cpus();
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}
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