Lokesh Vutla 166e5cc627 arm: omap: emif: Fix DDR3 init after warm reset ... EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>		2013-05-10 08:25:55 -04:00
..
cpu	arm: omap: emif: Fix DDR3 init after warm reset	2013-05-10 08:25:55 -04:00
dts	EXYNOS5: Add device node for DP	2013-03-27 21:23:18 +09:00
imx-common	imx: Add u-boot-with-nand-spl.imx make target	2013-04-12 07:55:08 +02:00
include/asm	OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5	2013-05-10 08:25:55 -04:00
lib	arm: Remove deprecated and now unused NAND SPL	2013-04-12 07:55:08 +02:00
config.mk	arm: Remove deprecated and now unused NAND SPL	2013-04-12 07:55:08 +02:00