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arm: omap: emif: Fix DDR3 init after warm reset

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EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2013-03-27 20:24:42 +00:00 committed by Tom Rini
parent 8ce4e5f932
commit 166e5cc627
1 changed files with 8 additions and 3 deletions
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11
arch/arm/cpu/armv7/omap-common/emif-common.c
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@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base)
else
ddr3_init(base, regs);
}
if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
emif_update_timings(base, regs);
@ -1262,10 +1267,10 @@ void sdram_init(void)
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
if (!(in_sdram || warm_reset())) {
if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
if (!in_sdram) {
if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
else
else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}