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![Rajeshwari Birje](/assets/img/avatar_default.png)
Adding the base patch for Exynos based SMDK5420. This shall enable compilation and basic boot support for SMDK5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
412 lines
8.8 KiB
C
412 lines
8.8 KiB
C
/*
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* (C) Copyright 2013 SAMSUNG Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <cros_ec.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <spi.h>
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#include <tmu.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/board.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <power/pmic.h>
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#include <asm/arch/sromc.h>
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#include <power/max77686_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct local_info {
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struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
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int cros_ec_err; /* Error for cros_ec, 0 if ok */
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};
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static struct local_info local;
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#if defined CONFIG_EXYNOS_TMU
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/* Boot Time Thermal Analysis for SoC temperature threshold breach */
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static void boot_temp_check(void)
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{
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int temp;
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switch (tmu_monitor(&temp)) {
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case TMU_STATUS_NORMAL:
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break;
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case TMU_STATUS_TRIPPED:
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/*
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* Status TRIPPED ans WARNING means corresponding threshold
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* breach
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*/
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puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
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set_ps_hold_ctrl();
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hang();
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break;
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case TMU_STATUS_WARNING:
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puts("EXYNOS_TMU: WARNING! Temperature very high\n");
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break;
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case TMU_STATUS_INIT:
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/*
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* TMU_STATUS_INIT means something is wrong with temperature
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* sensing and TMU status was changed back from NORMAL to INIT.
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*/
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puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
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break;
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default:
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debug("EXYNOS_TMU: Unknown TMU state\n");
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}
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
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#if defined CONFIG_EXYNOS_TMU
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if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
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debug("%s: Failed to init TMU\n", __func__);
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return -1;
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}
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boot_temp_check();
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#endif
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#ifdef CONFIG_EXYNOS_SPI
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spi_init();
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#endif
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return exynos_init();
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}
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int dram_init(void)
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{
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int i;
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u32 addr;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
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gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
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}
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return 0;
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}
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void dram_init_banksize(void)
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{
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int i;
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u32 addr, size;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
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size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
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gd->bd->bi_dram[i].start = addr;
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gd->bd->bi_dram[i].size = size;
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}
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}
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static int board_uart_init(void)
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{
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int err, uart_id, ret = 0;
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for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
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err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART%d not configured\n",
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(uart_id - PERIPH_ID_UART0));
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ret |= err;
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}
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}
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return ret;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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int err;
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err = board_uart_init();
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if (err) {
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debug("UART init failed\n");
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return err;
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}
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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board_i2c_init(gd->fdt_blob);
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#endif
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return err;
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}
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#endif
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struct cros_ec_dev *board_get_cros_ec_dev(void)
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{
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return local.cros_ec_dev;
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}
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#ifdef CONFIG_CROS_EC
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static int board_init_cros_ec_devices(const void *blob)
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{
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local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
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if (local.cros_ec_err)
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return -1; /* Will report in board_late_init() */
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return 0;
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}
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#endif
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#if defined(CONFIG_POWER)
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#ifdef CONFIG_POWER_MAX77686
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static int pmic_reg_update(struct pmic *p, int reg, uint regval)
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{
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u32 val;
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int ret = 0;
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ret = pmic_reg_read(p, reg, &val);
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if (ret) {
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debug("%s: PMIC %d register read failed\n", __func__, reg);
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return -1;
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}
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val |= regval;
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ret = pmic_reg_write(p, reg, val);
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if (ret) {
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debug("%s: PMIC %d register write failed\n", __func__, reg);
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return -1;
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}
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return 0;
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}
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static int max77686_init(void)
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{
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struct pmic *p;
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if (pmic_init(I2C_PMIC))
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return -1;
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p = pmic_get("MAX77686_PMIC");
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if (!p)
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return -ENODEV;
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if (pmic_probe(p))
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return -1;
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if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
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return -1;
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
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MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
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return -1;
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/* VDD_MIF */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
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MAX77686_BUCK1OUT_1V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK1OUT);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
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MAX77686_BUCK1CTRL_EN))
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return -1;
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/* VDD_ARM */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
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MAX77686_BUCK2DVS1_1_3V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK2DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
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MAX77686_BUCK2CTRL_ON))
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return -1;
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/* VDD_INT */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
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MAX77686_BUCK3DVS1_1_0125V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK3DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
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MAX77686_BUCK3CTRL_ON))
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return -1;
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/* VDD_G3D */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
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MAX77686_BUCK4DVS1_1_2V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK4DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
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MAX77686_BUCK3CTRL_ON))
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return -1;
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/* VDD_LDO2 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
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MAX77686_LD02CTRL1_1_5V | EN_LDO))
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return -1;
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/* VDD_LDO3 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
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MAX77686_LD03CTRL1_1_8V | EN_LDO))
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return -1;
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/* VDD_LDO5 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
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MAX77686_LD05CTRL1_1_8V | EN_LDO))
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return -1;
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/* VDD_LDO10 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
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MAX77686_LD10CTRL1_1_8V | EN_LDO))
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return -1;
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return 0;
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}
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#endif
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int power_init_board(void)
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{
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int ret = 0;
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set_ps_hold_ctrl();
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#ifdef CONFIG_POWER_MAX77686
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ret = max77686_init();
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#endif
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return ret;
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}
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#endif
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#ifdef CONFIG_OF_CONTROL
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static int decode_sromc(const void *blob, struct fdt_sromc *config)
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{
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int err;
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int node;
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node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
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if (node < 0) {
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debug("Could not find SROMC node\n");
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return node;
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}
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config->bank = fdtdec_get_int(blob, node, "bank", 0);
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config->width = fdtdec_get_int(blob, node, "width", 2);
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err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
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FDT_SROM_TIMING_COUNT);
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if (err < 0) {
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debug("Could not decode SROMC configuration Error: %s\n",
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fdt_strerror(err));
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return -FDT_ERR_NOTFOUND;
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}
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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u32 smc_bw_conf, smc_bc_conf;
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struct fdt_sromc config;
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fdt_addr_t base_addr;
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int node;
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node = decode_sromc(gd->fdt_blob, &config);
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if (node < 0) {
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debug("%s: Could not find sromc configuration\n", __func__);
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return 0;
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}
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node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
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if (node < 0) {
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debug("%s: Could not find lan9215 configuration\n", __func__);
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return 0;
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}
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/* We now have a node, so any problems from now on are errors */
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base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
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if (base_addr == FDT_ADDR_T_NONE) {
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debug("%s: Could not find lan9215 address\n", __func__);
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return -1;
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}
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/* Ethernet needs data bus width of 16 bits */
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if (config.width != 2) {
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debug("%s: Unsupported bus width %d\n", __func__,
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config.width);
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return -1;
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}
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smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
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| SROMC_BYTE_ENABLE(config.bank);
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smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
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SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
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SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
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SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
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SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
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SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
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SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
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/* Select and configure the SROMC bank */
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exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
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s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
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return smc911x_initialize(0, base_addr);
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#endif
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return 0;
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}
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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/* dwmmc initializattion for available channels */
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ret = exynos_dwmmc_init(gd->fdt_blob);
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if (ret)
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debug("dwmmc init failed\n");
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return ret;
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}
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#endif
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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stdio_print_current_devices();
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if (local.cros_ec_err) {
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/* Force console on */
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gd->flags &= ~GD_FLG_SILENT;
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printf("cros-ec communications failure %d\n",
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local.cros_ec_err);
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puts("\nPlease reset with Power+Refresh\n\n");
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panic("Cannot init cros-ec device");
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return -1;
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}
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return 0;
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}
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#endif
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int arch_early_init_r(void)
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{
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#ifdef CONFIG_CROS_EC
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if (board_init_cros_ec_devices(gd->fdt_blob)) {
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printf("%s: Failed to init EC\n", __func__);
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return 0;
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}
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#endif
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return 0;
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}
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