mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
ab5cda9f88
The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>
92 lines
3.0 KiB
C
92 lines
3.0 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 0: 64M Non-cacheable, guarded
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* 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 1: 1G Non-cacheable, guarded
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* 0x80000000 1G PCIE 8,9,a,b
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*/
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SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1G, 1),
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/*
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* TLB 2: 256M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 3: 256M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 4: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe100_0000 255M PCI IO range
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*/
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SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 5: 64M Non-cacheable, guarded
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* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
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*/
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SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_64M, 1),
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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