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3 Commits

Author SHA1 Message Date
Andy Fleming
ab5cda9f88 Remove LBC_CACHE_BASE from 8544 DS 
The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.

Signed-off-by: Andy Fleming <afleming@freescale.com>
 2008-07-14 11:21:33 -05:00
Kumar Gala
f69766e4b5 85xx: Add the concept of CFG_CCSRBAR_PHYS 
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 2008-03-26 11:43:03 -05:00
Kumar Gala
0f7a3dc95c 85xx: Convert MPC8544 DS to new TLB setup 
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 2008-01-17 02:05:35 -06:00