Simon Glass 112629c53a x86: Reduce mrccache record alignment size ... At present the records are 4KB in size. This is unnecessarily large when the SPI-flash erase size is 256 bytes. Reduce it so it will be more efficient with Apollo Lake's 24-byte variable-data record. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-12-15 11:44:12 +08:00
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cpu	x86: Define the SPL image start	2019-12-15 11:44:12 +08:00
dts	binman: x86: Separate out 16-bit reset and init code	2019-10-15 08:40:02 -06:00
include/asm	x86: Reduce mrccache record alignment size	2019-12-15 11:44:12 +08:00
lib	common: Move board_get_usable_ram_top() out of common.h	2019-12-02 18:25:04 -05:00
config.mk	x86: efi: app: Generate Microsoft PE format compliant image	2018-12-02 21:59:36 +01:00
Kconfig	x86: Drop RESET_SEG_SIZE	2019-10-11 17:37:34 +08:00
Makefile	x86: Allow 16-bit init to be in TPL	2019-05-08 13:02:13 +08:00