mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
fdff1f96a6
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
39 lines
642 B
Plaintext
39 lines
642 B
Plaintext
if TARGET_QEMU_VIRT
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config SYS_BOARD
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default "qemu-riscv"
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config SYS_VENDOR
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default "emulation"
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config SYS_CPU
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default "generic"
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config SYS_CONFIG_NAME
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default "qemu-riscv"
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config SYS_TEXT_BASE
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default 0x80000000 if !RISCV_SMODE
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default 0x80200000 if RISCV_SMODE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select GENERIC_RISCV
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imply SYS_NS16550
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imply VIRTIO_MMIO
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imply VIRTIO_NET
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imply VIRTIO_BLK
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imply CMD_PING
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imply CMD_FS_GENERIC
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imply DOS_PARTITION
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imply EFI_PARTITION
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imply ISO_PARTITION
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imply CMD_EXT2
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imply CMD_EXT4
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imply CMD_FAT
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imply BOARD_LATE_INIT
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imply OF_BOARD_SETUP
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imply SIFIVE_SERIAL
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endif
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