York Sun ed7a3943d5 armv8: fsl-layerscape: mmu: Fix enabling MMU ... MMU bit in SCTLR needs to be set explicitly after tables are created. It isn't an issue for EL3 becuase this bit is already set by early MMU setup. But for other exception levels this bit was not set. Signed-off-by: York Sun <york.sun@nxp.com>		2016-07-26 09:03:06 -07:00
..
doc	armv8: fsl_lsch2: Add LS1046A SoC support	2016-07-26 09:02:23 -07:00
cpu.c	armv8: fsl-layerscape: mmu: Fix enabling MMU	2016-07-26 09:03:06 -07:00
cpu.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
fdt.c	ARMv8/Layerscape: switch SMP method accordingly	2016-07-19 11:34:00 -07:00
fsl_lsch2_serdes.c	armv8: fsl_lsch2: Add SerDes 2 support	2016-07-26 09:02:16 -07:00
fsl_lsch2_speed.c	armv8: fsl_lsch2: Add LS1046A SoC support	2016-07-26 09:02:23 -07:00
fsl_lsch3_serdes.c	fsl_*_serdes.c: Modify memset call in serdes_init	2015-12-13 18:27:29 -08:00
fsl_lsch3_speed.c	Fix various typos, scattered over the code.	2016-05-05 21:39:26 -04:00
lowlevel.S	armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC	2016-06-03 14:12:50 -07:00
ls1012a_serdes.c	armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC	2016-06-03 14:12:50 -07:00
ls1043a_serdes.c	armv8/ls1043ardb: Add LS1043ARDB board support	2015-10-29 10:34:01 -07:00
ls1046a_serdes.c	armv8: fsl_lsch2: Add LS1046A SoC support	2016-07-26 09:02:23 -07:00
ls2080a_serdes.c	armv8: fsl-layerscape: Updating entries in Serdes Table	2016-03-21 12:42:13 -07:00
Makefile	armv8: fsl_lsch2: Add LS1046A SoC support	2016-07-26 09:02:23 -07:00
mp.c	armv8: fsl-layerscape: Fix "cpu release" command	2015-11-30 09:11:12 -08:00
ppa.c	ARMv8/layerscape: Add FSL PPA support	2016-07-19 11:33:53 -07:00
soc.c	armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs	2016-06-28 12:08:53 -07:00
spl.c	common: Pass the boot device into spl_boot_mode()	2016-06-26 20:17:22 +02:00