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f588b4d205
Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux
142 lines
2.0 KiB
Plaintext
142 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale ls1021a TWR board common device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*/
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#include "ls1021a.dtsi"
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/ {
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model = "LS1021A TWR Board";
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aliases {
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enet2-rgmii-phy = &rgmii_phy1;
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enet0-sgmii-phy = &sgmii_phy2;
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enet1-sgmii-phy = &sgmii_phy0;
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spi0 = &qspi;
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spi1 = &dspi1;
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: n25q128a13@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&dspi1 {
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bus-num = <0>;
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status = "okay";
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dspiflash: at26df081a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&enet0 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&enet1 {
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tbi-handle = <&tbi1>;
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phy-handle = <&sgmii_phy0>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&enet2 {
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR Flash on board */
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ranges = <0x0 0x0 0x60000000 0x08000000>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&mdio0 {
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sgmii_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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/* SGMII PCS for enet0 */
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tbi0: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&mdio1 {
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/* SGMII PCS for enet1 */
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tbi1: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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