Siarhei Siamashka 013f2d7469 sunxi: dram: Use divisor P=1 for PLL5 ... This configures the PLL5P clock frequency to something in the ballpark of 1GHz and allows more choices for MBUS and G2D clock frequency selection (using their own divisors). In particular, it enables the use of 2/3 clock speed ratio between MBUS and DRAM. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>		2014-08-12 08:42:33 +02:00
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board.c	sunxi: Add CONFIG_MACPWR option	2014-07-31 15:37:23 +02:00
clock_sun4i.c	ahci: provide sunxi SATA driver using AHCI platform framework	2014-07-31 15:37:22 +02:00
clock.c	sunxi: add sun7i clocks and timer support.	2014-05-25 16:12:12 +02:00
config.mk	sunxi: non-FEL SPL boot support for sun7i	2014-05-25 16:31:03 +02:00
cpu_info.c	sunxi: Add sun5i support	2014-07-06 20:12:44 +01:00
dram.c	sunxi: dram: Use divisor P=1 for PLL5	2014-08-12 08:42:33 +02:00
Makefile	sunxi: HYP/non-sec: add sun7i PSCI backend	2014-07-31 15:37:24 +02:00
pinmux.c	sunxi: add sun7i pinmux and gpio support	2014-05-25 16:12:21 +02:00
psci.S	sunxi: HYP/non-sec: add sun7i PSCI backend	2014-07-31 15:37:24 +02:00
start.c	sunxi: add sun7i cpu, board and start of day support	2014-05-25 16:12:40 +02:00
timer.c	sunxi: add sun7i clocks and timer support.	2014-05-25 16:12:12 +02:00
u-boot-spl-fel.lds	sunxi: Add i2c support	2014-07-18 19:41:30 +01:00
u-boot-spl.lds	sunxi: Add i2c support	2014-07-18 19:41:30 +01:00