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https://github.com/brain-hackers/u-boot-brain
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0963060c99
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063). CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0 Working: - Eth0 - i2C - MMC/SD - NAND - UART (1 & 5) - USB (host & otg) Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
8 lines
129 B
Makefile
8 lines
129 B
Makefile
# Copyright (C) 2018 Collabora Ltd.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := pcl063.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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