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https://github.com/brain-hackers/u-boot-brain
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99e555a79a
This device has a large set of ACPI tables. Bring these in from coreboot so that full functionality is available (apart from SMI). Signed-off-by: Simon Glass <sjg@chromium.org>
61 lines
1.2 KiB
Plaintext
61 lines
1.2 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Google Inc.
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*/
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#include "variant_ec.h"
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#include "variant_gpio.h"
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#include <acpi/acpi_table.h>
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#include <asm/acpi/global_nvs.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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OEM_TABLE_ID,
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <asm/arch/acpi/globalnvs.asl>
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/* CPU */
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#include <asm/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <asm/arch/acpi/northbridge.asl>
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#include <asm/arch/acpi/southbridge.asl>
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#include <asm/arch/acpi/pch_hda.asl>
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}
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}
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/* Chrome OS specific */
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#include <asm/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <asm/acpi/sleepstates.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <asm/acpi/cros_ec/superio.asl>
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/* ACPI code for EC functions */
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#include <asm/acpi/cros_ec/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include "variant_dptf.asl"
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/* Include soc specific DPTF changes */
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#include <asm/arch/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <asm/acpi/dptf/dptf.asl>
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}
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}
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