mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
x86: coral: Add ACPI tables for coral
This device has a large set of ACPI tables. Bring these in from coreboot so that full functionality is available (apart from SMI). Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Bin Meng
parent
7924b499a2
commit
99e555a79a
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@ -3,3 +3,4 @@
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# Copyright 2019 Google LLC
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obj-y += coral.o
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obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
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71
board/google/chromebook_coral/baseboard_dptf.asl
Normal file
71
board/google/chromebook_coral/baseboard_dptf.asl
Normal file
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@ -0,0 +1,71 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*/
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#define DPTF_CPU_PASSIVE 95
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#define DPTF_CPU_CRITICAL 105
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Battery"
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#define DPTF_TSR0_PASSIVE 120
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#define DPTF_TSR0_CRITICAL 125
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Ambient"
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#define DPTF_TSR1_PASSIVE 46
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#define DPTF_TSR1_CRITICAL 75
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Charger"
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#define DPTF_TSR2_PASSIVE 58
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#define DPTF_TSR2_CRITICAL 90
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#define DPTF_ENABLE_CHARGER
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
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Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
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})
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
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/* CPU Effect on Temp Sensor 0 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
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#ifdef DPTF_ENABLE_CHARGER
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/* Charger Effect on Temp Sensor 2 */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
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#endif
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/* CPU Effect on Temp Sensor 1 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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3000, /* PowerLimitMinimum */
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12000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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8000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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@ -4,7 +4,24 @@
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*/
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#include <common.h>
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#include <bloblist.h>
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#include <command.h>
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#include <dm.h>
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#include <log.h>
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#include <acpi/acpigen.h>
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#include <asm-generic/gpio.h>
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#include <asm/acpi_nhlt.h>
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#include <asm/intel_gnvs.h>
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#include <asm/intel_pinctrl.h>
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#include <dm/acpi.h>
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#include "variant_gpio.h"
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struct cros_gpio_info {
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const char *linux_name;
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enum cros_gpio_t type;
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int gpio_num;
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int flags;
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};
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int arch_misc_init(void)
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{
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@ -18,3 +35,122 @@ int board_run_command(const char *cmdline)
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return 0;
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}
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int chromeos_get_gpio(const struct udevice *dev, const char *prop,
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enum cros_gpio_t type, struct cros_gpio_info *info)
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{
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struct udevice *pinctrl;
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struct gpio_desc desc;
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int ret;
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ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0);
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if (ret == -ENOTBLK)
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info->gpio_num = CROS_GPIO_VIRTUAL;
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else if (ret)
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return log_msg_ret("gpio", ret);
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else
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info->gpio_num = desc.offset;
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info->linux_name = dev_read_string(desc.dev, "linux-name");
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if (!info->linux_name)
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return log_msg_ret("linux-name", -ENOENT);
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info->type = type;
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/* Get ACPI pin from GPIO library if available */
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if (info->gpio_num != CROS_GPIO_VIRTUAL) {
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pinctrl = dev_get_parent(desc.dev);
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info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl,
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info->gpio_num);
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}
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info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW :
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CROS_GPIO_ACTIVE_HIGH;
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return 0;
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}
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static int chromeos_acpi_gpio_generate(const struct udevice *dev,
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struct acpi_ctx *ctx)
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{
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struct cros_gpio_info info[3];
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int count, i;
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int ret;
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count = 3;
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ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]);
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if (ret)
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return log_msg_ret("rec", ret);
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ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP,
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&info[1]);
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if (ret)
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return log_msg_ret("rec", ret);
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ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE,
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&info[2]);
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if (ret)
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return log_msg_ret("rec", ret);
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acpigen_write_scope(ctx, "\\");
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acpigen_write_name(ctx, "OIPG");
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acpigen_write_package(ctx, count);
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for (i = 0; i < count; i++) {
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acpigen_write_package(ctx, 4);
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acpigen_write_integer(ctx, info[i].type);
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acpigen_write_integer(ctx, info[i].flags);
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acpigen_write_integer(ctx, info[i].gpio_num);
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acpigen_write_string(ctx, info[i].linux_name);
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acpigen_pop_len(ctx);
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}
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acpigen_pop_len(ctx);
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acpigen_pop_len(ctx);
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return 0;
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}
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static int coral_write_acpi_tables(const struct udevice *dev,
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struct acpi_ctx *ctx)
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{
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struct acpi_global_nvs *gnvs;
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struct nhlt *nhlt;
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const char *oem_id = "coral";
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const char *oem_table_id = "coral";
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u32 oem_revision = 3;
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int ret;
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gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs));
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if (!gnvs)
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return log_msg_ret("bloblist", -ENOENT);
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nhlt = nhlt_init();
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if (!nhlt)
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return -ENOMEM;
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log_debug("Setting up NHLT\n");
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ret = acpi_setup_nhlt(ctx, nhlt);
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if (ret)
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return log_msg_ret("setup", ret);
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/* Update NHLT GNVS Data */
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gnvs->nhla = (uintptr_t)ctx->current;
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gnvs->nhll = nhlt_current_size(nhlt);
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ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id,
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oem_revision);
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if (ret)
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return log_msg_ret("serialise", ret);
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return 0;
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}
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struct acpi_ops coral_acpi_ops = {
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.write_tables = coral_write_acpi_tables,
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.inject_dsdt = chromeos_acpi_gpio_generate,
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};
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static const struct udevice_id coral_ids[] = {
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{ .compatible = "google,coral" },
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{ }
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};
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U_BOOT_DRIVER(coral_drv) = {
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.name = "coral",
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.id = UCLASS_BOARD,
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.of_match = coral_ids,
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ACPI_OPS_PTR(&coral_acpi_ops)
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};
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60
board/google/chromebook_coral/dsdt.asl
Normal file
60
board/google/chromebook_coral/dsdt.asl
Normal file
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@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Google Inc.
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*/
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#include "variant_ec.h"
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#include "variant_gpio.h"
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#include <acpi/acpi_table.h>
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#include <asm/acpi/global_nvs.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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OEM_TABLE_ID,
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0x20110725 // OEM revision
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)
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{
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/* global NVS and variables */
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#include <asm/arch/acpi/globalnvs.asl>
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/* CPU */
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#include <asm/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <asm/arch/acpi/northbridge.asl>
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#include <asm/arch/acpi/southbridge.asl>
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#include <asm/arch/acpi/pch_hda.asl>
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}
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}
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/* Chrome OS specific */
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#include <asm/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <asm/acpi/sleepstates.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <asm/acpi/cros_ec/superio.asl>
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/* ACPI code for EC functions */
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#include <asm/acpi/cros_ec/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include "variant_dptf.asl"
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/* Include soc specific DPTF changes */
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#include <asm/arch/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <asm/acpi/dptf/dptf.asl>
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}
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}
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6
board/google/chromebook_coral/variant_dptf.asl
Normal file
6
board/google/chromebook_coral/variant_dptf.asl
Normal file
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@ -0,0 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Google Inc.
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*/
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#include "baseboard_dptf.asl"
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75
board/google/chromebook_coral/variant_ec.h
Normal file
75
board/google/chromebook_coral/variant_ec.h
Normal file
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@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 Google LLC
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/*
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* Taken from coreboot file of the same name
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*/
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include "variant_gpio.h"
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#include <ec_commands.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
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#define MAINBOARD_EC_SMI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
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/* EC can wake from S5 with lid or power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with lid or power button or key press */
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#define MAINBOARD_EC_S3_WAKE_EVENTS \
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(MAINBOARD_EC_S5_WAKE_EVENTS |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/* Enable LID switch and provide wake pin for EC */
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#define EC_ENABLE_LID_SWITCH
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define EC_ENABLE_TBMC_DEVICE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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/* Enable EC backed Keyboard Backlight in ACPI */
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#define EC_ENABLE_KEYBOARD_BACKLIGHT
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#endif
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63
board/google/chromebook_coral/variant_gpio.h
Normal file
63
board/google/chromebook_coral/variant_gpio.h
Normal file
|
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@ -0,0 +1,63 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 Google LLC
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*
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* Taken from coreboot file of the same name
|
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*/
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#ifndef BASEBOARD_GPIO_H
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#define BASEBOARD_GPIO_H
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#include <asm/arch/gpio.h>
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#include <ec_commands.h>
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/*
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* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
|
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* which is North community
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*/
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#define EC_SCI_GPI GPE0_DW1_11
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/* EC SMI */
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#define EC_SMI_GPI GPIO_49
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/*
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* On lidopen/lidclose GPIO_22 from North Community gets toggled and
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* is used in _PRW to wake up device from sleep. GPIO_22 maps to
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* group GPIO_GPE_N_31_0 and the pad is configured as SCI with
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* EDGE_SINGLE and INVERT.
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*/
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#define GPE_EC_WAKE GPE0_DW1_22
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/* Write Protect and indication if EC is in RW code. */
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#define GPIO_PCH_WP GPIO_75
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#define GPIO_EC_IN_RW GPIO_41
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/* Determine if board is in final shipping mode. */
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#define GPIO_SHIP_MODE GPIO_10
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/* Memory SKU GPIOs. */
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#define MEM_CONFIG3 GPIO_45
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#define MEM_CONFIG2 GPIO_38
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#define MEM_CONFIG1 GPIO_102
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#define MEM_CONFIG0 GPIO_101
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/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
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#define DMIC_CONFIG_PIN GPIO_17
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#ifndef __ASSEMBLY__
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enum cros_gpio_t {
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CROS_GPIO_REC = 1, /* Recovery */
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/* Developer; * deprecated (chromium:942901) */
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CROS_GPIO_DEPRECATED_DEV = 2,
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CROS_GPIO_WP = 3, /* Write Protect */
|
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CROS_GPIO_PE = 4, /* Phase enforcement for final product */
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CROS_GPIO_ACTIVE_LOW = 0,
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CROS_GPIO_ACTIVE_HIGH = 1,
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CROS_GPIO_VIRTUAL = -1,
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};
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#endif
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#endif /* BASEBOARD_GPIO_H */
|
||||
|
|
@ -27,6 +27,11 @@ enum bloblist_tag_t {
|
|||
BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */
|
||||
BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */
|
||||
BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */
|
||||
/*
|
||||
* Advanced Configuration and Power Interface Global Non-Volatile
|
||||
* Sleeping table. This forms part of the ACPI tables passed to Linux.
|
||||
*/
|
||||
BLOBLISTT_ACPI_GNVS,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user