mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
bc24884c4c
It turns out that there is a magic bit in PRCM region which seemingly
makes PLLs work if it's enabled. Sadly, there is no documentation what
it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
before any clock is set up.
Fixes: b18bd53d6c ("sunxi: introduce support for H616 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/prcm.h>
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#ifdef CONFIG_SPL_BUILD
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void clock_init_safe(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* this seems to enable PLLs on H616 */
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if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
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setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
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clock_set_pll1(408000000);
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writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
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while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
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;
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clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
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CCM_CPU_AXI_DEFAULT_FACTORS);
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writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
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writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
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writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
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/*
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* The mux and factor are set, but the clock will be enabled in
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* DRAM initialization code.
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*/
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writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
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}
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#endif
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void clock_init_uart(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* uart clock source is apb2 */
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writel(APB2_CLK_SRC_OSC24M|
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APB2_CLK_RATE_N_1|
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APB2_CLK_RATE_M(1),
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&ccm->apb2_cfg);
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/* open the clock for uart */
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setbits_le32(&ccm->uart_gate_reset,
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1 << (CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->uart_gate_reset,
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1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
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}
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#ifdef CONFIG_SPL_BUILD
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void clock_set_pll1(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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u32 val;
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/* Do not support clocks < 288MHz as they need factor P */
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if (clk < 288000000) clk = 288000000;
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/* Switch to 24MHz clock while changing PLL1 */
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val = readl(&ccm->cpu_axi_cfg);
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val &= ~CCM_CPU_AXI_MUX_MASK;
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val |= CCM_CPU_AXI_MUX_OSC24M;
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writel(val, &ccm->cpu_axi_cfg);
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/* clk = 24*n/p, p is ignored if clock is >288MHz */
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
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#ifdef CONFIG_MACH_SUN50I_H616
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CCM_PLL1_OUT_EN |
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#endif
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CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
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while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
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/* Switch CPU to PLL1 */
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val = readl(&ccm->cpu_axi_cfg);
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val &= ~CCM_CPU_AXI_MUX_MASK;
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val |= CCM_CPU_AXI_MUX_PLL_CPUX;
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writel(val, &ccm->cpu_axi_cfg);
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}
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#endif
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unsigned int clock_get_pll6(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
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uint32_t rval = readl(&ccm->pll6_cfg);
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int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
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int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
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CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
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int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
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CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
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/* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
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return 24000000 / m * n / div1 / div2;
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}
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int clock_twi_onoff(int port, int state)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_prcm_reg *const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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u32 value, *ptr;
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int shift;
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value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
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if (port == 5) {
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shift = 0;
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ptr = &prcm->twi_gate_reset;
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} else {
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shift = port;
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ptr = &ccm->twi_gate_reset;
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}
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/* set the apb clock gate and reset for twi */
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if (state)
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setbits_le32(ptr, value << shift);
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else
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clrbits_le32(ptr, value << shift);
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return 0;
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}
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