mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1d6c54ecb3
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
74 lines
1.2 KiB
Plaintext
74 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP R5
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*
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* (C) Copyright 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynqmp-r5";
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model = "Xilinx ZynqMP R5";
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cpu@0 {
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compatible = "arm,cortex-r5";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart1;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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chosen {
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bootargs = "";
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stdout-path = "serial0:115200n8";
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};
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clk100: clk100 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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u-boot,dm-pre-reloc;
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};
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amba {
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u-boot,dm-pre-reloc;
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ttc0: timer@ff110000 {
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compatible = "cdns,ttc";
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status = "okay";
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reg = <0xff110000 0x1000>;
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timer-width = <32>;
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clocks = <&clk100>;
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};
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uart1: serial@ff010000 {
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u-boot,dm-pre-reloc;
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compatible = "cdns,uart-r1p12", "xlnx,xuartps";
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reg = <0xff010000 0x1000>;
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clock-names = "uart_clk", "pclk";
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clocks = <&clk100 &clk100>;
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};
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};
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};
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