317 lines
8.7 KiB
Plaintext
317 lines
8.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal a2197 RevA System Controller on MGT
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*
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* (C) Copyright 2019, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Versal System Controller on a2197 MGT Char board RevA";
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compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
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"xlnx,zynqmp-a2197", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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mmc0 = &sdhci0;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &dcc;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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xlnx,eeprom = <&eeprom>;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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ina226-u74 {
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compatible = "iio-hwmon";
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io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
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};
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ina226-u75 {
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compatible = "iio-hwmon";
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io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
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};
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ina226-u78 {
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compatible = "iio-hwmon";
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io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
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};
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ina226-u79 {
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compatible = "iio-hwmon";
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io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
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};
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ina226-u82 {
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compatible = "iio-hwmon";
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io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;
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};
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ina226-u84 {
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compatible = "iio-hwmon";
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io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
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};
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};
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&sdhci0 { /* emmc MIO 13-23 16GB */
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status = "okay";
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non-removable;
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disable-wp;
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bus-width = <8>;
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xlnx,mio-bank = <0>;
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&gem0 { /* eth MDIO 76/77 */
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "sgmii";
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is-internal-pcspma;
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phy0: ethernet-phy@0 { /* marwell m88e1512 */
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reg = <0>;
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reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
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/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "", "", "", "", "", /* 0 - 4 */
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"", "", "", "", "", /* 5 - 9 */
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"", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
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"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
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"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
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"", "", "", "", "", /* 25 - 29 */
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"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
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"LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
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"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
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"", "", "", "", "", /* 45 - 49 */
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"", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
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"", "", "", "", "", /* 65 - 69 */
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"", "", "", "", "", /* 70 - 74 */
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"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
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"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
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"SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
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"SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
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"SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
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"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
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"SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
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"SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
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"SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
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"SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
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"SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
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"PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
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"TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
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"PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
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"MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 174 */
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};
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&i2c0 { /* MIO 34-35 - can't stay here */
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status = "okay";
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clock-frequency = <400000>;
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scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
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i2c-mux@74 { /* u94 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* Use for storing information about SC board */
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eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */
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compatible = "atmel,24c32";
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reg = <0x50>;
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};
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};
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i2c@1 { /* CM_I2C_SCL - Samtec */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c@2 { /* PMBUS - AFX_PMBUS */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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tps544@d { /* u85 */
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compatible = "ti,tps544b25";
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reg = <0xd>;
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};
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tps544@10 { /* u73 */
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compatible = "ti,tps544b25";
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reg = <0x10>;
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};
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tps544@11 { /* u76 */
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compatible = "ti,tps544b25";
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reg = <0x11>;
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};
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tps544@12 { /* u77 */
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compatible = "ti,tps544b25";
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reg = <0x12>;
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};
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tps544@13 { /* u80 */
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compatible = "ti,tps544b25";
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reg = <0x13>;
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};
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tps544@14 { /* u81 */
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compatible = "ti,tps544b25";
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reg = <0x14>;
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};
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tps544@15 { /* u83 */
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compatible = "ti,tps544b25";
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reg = <0x15>;
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};
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tps544@16 { /* u63 */
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compatible = "ti,tps544b25";
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reg = <0x16>;
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};
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tps544@17 { /* u66 */
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compatible = "ti,tps544b25";
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reg = <0x17>;
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};
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tps544@18 { /* u67 */
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compatible = "ti,tps544b25";
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reg = <0x18>;
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};
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tps544@19 { /* u69 */
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compatible = "ti,tps544b25";
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reg = <0x19>;
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};
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tps544@1d { /* u88 */
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compatible = "ti,tps544b25";
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reg = <0x1d>;
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};
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tps544@1e { /* u89 */
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compatible = "ti,tps544b25";
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reg = <0x1e>;
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};
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tps544@1f { /* u87 */
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compatible = "ti,tps544b25";
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reg = <0x1f>;
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};
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tps544@20 { /* u71 */
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compatible = "ti,tps544b25";
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reg = <0x20>;
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};
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u74: ina226@40 { /* u74 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u74";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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u75: ina226@41 { /* u75 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u75";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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u78: ina226@42 { /* u78 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u78";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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u79: ina226@43 { /* u79 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u79";
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reg = <0x43>;
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shunt-resistor = <1000>;
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};
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u82: ina226@44 { /* u82 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u82";
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reg = <0x44>;
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shunt-resistor = <1000>;
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};
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u84: ina226@45 { /* u84 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u84";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
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compatible = "ti,tps53681", "ti,tps53679";
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reg = <0xc0>;
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};
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};
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i2c@3 { /* fmc1 via JA2G */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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eeprom_fmc1: eeprom@50 { /* on FMC */
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compatible = "atmel,24c04";
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reg = <0x50>;
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};
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};
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i2c@4 { /* fmc2 via JA3G */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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eeprom_fmc2: eeprom@50 { /* on FMC */
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compatible = "atmel,24c04";
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reg = <0x50>;
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};
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};
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i2c@5 { /* fmc3 via JA4G */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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eeprom_fmc3: eeprom@50 { /* on FMC */
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compatible = "atmel,24c04";
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reg = <0x50>;
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};
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};
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i2c@6 { /* ddr dimm */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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/* 7 unused */
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};
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};
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&usb0 { /* USB0 MIO52-63 */
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status = "okay";
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xlnx,usb-polarity = <0>;
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xlnx,usb-reset-mode = <0>;
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "peripheral";
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maximum-speed = "high-speed";
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};
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