90 lines
1.8 KiB
Plaintext
90 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal a2197 RevA System Controller
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*
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* (C) Copyright 2019, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Versal System Controller on a2197 board RevA";
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compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp";
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aliases {
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i2c0 = &i2c0;
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serial0 = &uart0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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clock-frequency = <400000>;
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i2c-mux@74 { /* this cover MGT board */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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u-boot,dm-pre-reloc;
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/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* Use for storing information about SC board */
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eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */
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compatible = "atmel,24c32";
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u-boot,dm-pre-reloc;
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reg = <0x50>;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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u-boot,dm-pre-reloc;
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clock-frequency = <400000>;
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i2c-mux@74 { /* This cover processor board */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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u-boot,dm-pre-reloc;
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/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* Use for storing information about SC board */
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eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */
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compatible = "atmel,24c32";
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u-boot,dm-pre-reloc;
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reg = <0x50>;
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};
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};
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};
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};
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