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a7fdac7e2a
Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
39 lines
820 B
Plaintext
39 lines
820 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device tree fragment for RCW SCH-30841 card
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*
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* Copyright 2019-2021 NXP Semiconductors
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*/
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/*
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* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
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* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
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* together on a single lane or mapped 1:1 to serdes lanes.
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* It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
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* PHY addresses are 0x00 - 0x03.
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* On the card the first port is the bottom port (closest to PEX connector).
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*/
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phy@00 {
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reg = <0x00>;
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mdi-reversal = <1>;
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smb-addr = <0x25>;
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};
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phy@01 {
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reg = <0x01>;
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mdi-reversal = <1>;
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smb-addr = <0x26>;
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};
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phy@02 {
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reg = <0x02>;
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mdi-reversal = <1>;
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smb-addr = <0x27>;
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};
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phy@03 {
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reg = <0x03>;
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mdi-reversal = <1>;
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smb-addr = <0x28>;
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};
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