101 lines
1.7 KiB
Plaintext
101 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7
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*
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* Some assumptions are made:
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* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
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* * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac3 {
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status = "okay";
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phy-handle = <&aquantia_phy1>;
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phy-connection-type = "usxgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&aquantia_phy2>;
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phy-connection-type = "usxgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&aquantia_phy3>;
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phy-connection-type = "usxgmii";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&aquantia_phy4>;
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phy-connection-type = "usxgmii";
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};
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&dpmac7 {
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status = "okay";
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phy-handle = <&sgmii_phy1>;
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phy-connection-type = "sgmii";
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};
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&dpmac8 {
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status = "okay";
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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};
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&dpmac9 {
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status = "okay";
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phy-handle = <&sgmii_phy3>;
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phy-connection-type = "sgmii";
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};
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&dpmac10 {
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status = "okay";
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phy-handle = <&sgmii_phy4>;
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phy-connection-type = "sgmii";
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};
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&emdio1_slot1 {
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aquantia_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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aquantia_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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aquantia_phy3: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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aquantia_phy4: ethernet-phy@7 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x3>;
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};
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};
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&emdio1_slot2 {
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sgmii_phy1: ethernet-phy@1c {
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reg = <0x1c>;
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};
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sgmii_phy2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmii_phy3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmii_phy4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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