mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
cc32fd911a
The definition follows the DSA binding in kernel and describes the switch, its ports and PHYs. The switch node has the same structure as in Linux and this patch enables it (and relevant ports) for the LS1028A RDB board. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is not used in U-Boot and was disabled. Ethernet port aliases were also added to better manage the multitude of ports available now. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
484 lines
11 KiB
Plaintext
484 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1028a SOC common device tree source
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*
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* Copyright 2019-2020 NXP
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1028a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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clockgen: clocking@1300000 {
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compatible = "fsl,ls1028a-clockgen";
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reg = <0x0 0x1300000 0x0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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memory@01080000 {
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device_type = "memory";
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reg = <0x00000000 0x01080000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06040000 0 0x40000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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gic_lpi_base: syscon@0x80000000 {
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compatible = "gic-lpi-base";
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reg = <0x0 0x80000000 0x0 0x100000>;
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max-gic-redistributors = <2>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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fspi: flexspi@20c0000 {
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compatible = "nxp,lx2160a-fspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "fspi_base", "fspi_mmap";
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "fspi_en", "fspi";
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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serial0: serial@21c0500 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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serial1: serial@21c0600 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pcie1: pcie@3400000 {
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compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000
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0x00 0x03480000 0x0 0x40000 /* lut registers */
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0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
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0x80 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie2: pcie@3500000 {
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compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x80000
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0x00 0x03580000 0x0 0x40000 /* lut registers */
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0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
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0x88 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@1f0000000 {
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compatible = "pci-host-ecam-generic";
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/* ECAM bus 0, HW has more space reserved but not populated */
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bus-range = <0x0 0x0>;
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reg = <0x01 0xf0000000 0x0 0x100000>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
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enetc0: pci@0,0 {
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reg = <0x000000 0 0 0 0>;
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status = "disabled";
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};
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enetc1: pci@0,1 {
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reg = <0x000100 0 0 0 0>;
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status = "disabled";
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};
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enetc2: pci@0,2 {
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reg = <0x000200 0 0 0 0>;
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status = "okay";
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phy-mode = "internal";
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};
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mdio0: pci@0,3 {
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#address-cells=<0>;
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#size-cells=<1>;
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reg = <0x000300 0 0 0 0>;
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status = "disabled";
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};
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mscc_felix: pci@0,5 {
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reg = <0x000500 0 0 0 0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mscc_felix_port0: port@0 {
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reg = <0>;
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status = "disabled";
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};
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mscc_felix_port1: port@1 {
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reg = <1>;
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status = "disabled";
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};
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mscc_felix_port2: port@2 {
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reg = <2>;
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status = "disabled";
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};
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mscc_felix_port3: port@3 {
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reg = <3>;
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status = "disabled";
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};
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mscc_felix_port4: port@4 {
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reg = <4>;
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phy-mode = "internal";
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status = "disabled";
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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mscc_felix_port5: port@5 {
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reg = <5>;
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phy-mode = "internal";
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status = "disabled";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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enetc6: pci@0,6 {
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reg = <0x000600 0 0 0 0>;
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status = "disabled";
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phy-mode = "internal";
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};
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c1: i2c@2010000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c2: i2c@2020000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c3: i2c@2030000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c4: i2c@2040000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2040000 0x0 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c5: i2c@2050000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2050000 0x0 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c6: i2c@2060000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2060000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c7: i2c@2070000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2070000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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lpuart0: serial@2260000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2260000 0x0 0x1000>;
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interrupts = <0 232 0x4>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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little-endian;
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status = "disabled";
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};
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lpuart1: serial@2270000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2270000 0x0 0x1000>;
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interrupts = <0 233 0x4>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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little-endian;
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status = "disabled";
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};
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lpuart2: serial@2280000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2280000 0x0 0x1000>;
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interrupts = <0 234 0x4>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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little-endian;
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status = "disabled";
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};
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lpuart3: serial@2290000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2290000 0x0 0x1000>;
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interrupts = <0 235 0x4>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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little-endian;
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status = "disabled";
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};
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lpuart4: serial@22a0000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x22a0000 0x0 0x1000>;
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interrupts = <0 236 0x4>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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little-endian;
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status = "disabled";
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};
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lpuart5: serial@22b0000 {
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x22b0000 0x0 0x1000>;
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interrupts = <0 237 0x4>;
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clocks = <&sysclk>;
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clock-names = "ipg";
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little-endian;
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status = "disabled";
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};
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usb1: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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status = "disabled";
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};
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usb2: usb3@3110000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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status = "disabled";
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <5>;
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litte-endian;
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status = "disabled";
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <5>;
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little-endian;
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status = "disabled";
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};
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dspi2: dspi@2120000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2120000 0x0 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <5>;
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little-endian;
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status = "disabled";
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};
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esdhc0: esdhc@2140000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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big-endian;
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bus-width = <4>;
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status = "disabled";
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};
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esdhc1: esdhc@2150000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2150000 0x0 0x10000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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big-endian;
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non-removable;
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bus-width = <4>;
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status = "disabled";
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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little-endian;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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little-endian;
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};
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gpio2: gpio@2320000 {
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compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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little-endian;
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1028a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
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reg-names = "sata-base", "ecc-addr";
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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cluster1_core0_watchdog: wdt@c000000 {
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compatible = "arm,sp805-wdt";
|
|
reg = <0x0 0xc000000 0x0 0x1000>;
|
|
};
|
|
};
|