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https://github.com/brain-hackers/u-boot-brain
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AST2600 is the 7th generation of Aspeed SoC designated for Interated Remote Management Processor. AST2600 has significant performance improvement by integrating 1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the controllers are also improved with more features and better performance than preceding AST24xx/AST25xx. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
45 lines
886 B
Plaintext
45 lines
886 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/clock/ast2600-clock.h>
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#include <dt-bindings/reset/ast2600-reset.h>
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#include "ast2600.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2600-scu";
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reg = <0x1e6e2000 0x1000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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#reset-cells = <1>;
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uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
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};
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rst: reset-controller {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2600-reset";
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aspeed,wdt = <&wdt1>;
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2600-sdrammc";
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reg = <0x1e6e0000 0x100
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0x1e6e0100 0x300
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0x1e6e0400 0x200 >;
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#reset-cells = <1>;
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clocks = <&scu ASPEED_CLK_MPLL>;
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resets = <&rst ASPEED_RESET_SDRAM>;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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};
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};
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};
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