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a0ba97e561
Use a single dtsi file for CP110 die instead of master/slave. Moving to single file will allow miltiple DTSI inclusions with re-defined CP index and name. This change will also allow support for SoCs containing more than two CP110 dies on board. Move pin control definitions from CP110 DTS to board DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
19 lines
659 B
Plaintext
19 lines
659 B
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 - 2021 Marvell International Ltd.
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*/
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/* Common definitions used by Armada 8K DTs */
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/* This defines used to calculate the base address of each CP */
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#define CP110_BASE_OFFSET (0xf2000000)
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#define CP110_SPACE_SIZE (0x02000000)
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#define CP110_BASE (CP110_BASE_OFFSET + \
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((CP110_NUM % 2) * CP110_SPACE_SIZE))
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#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
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#define CP110_PCIEx_CPU_MEM_BASE(iface) \
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(0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) * 0x1000000)
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#define CP110_PCIEx_BUS_MEM_BASE(iface) \
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(CP110_PCIEx_CPU_MEM_BASE(iface))
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#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
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