The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006090742000024 "Add support for multiple I2C buses"
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
CHANGELOG:
* Add support for the Freescale MPC8349E-mITX reference design platform.
The second TSEC (Vitesse 7385 switch) is not supported at this time.
Signed-off-by: Timur Tabi <timur@freescale.com>
CHANGELOG:
* Errata DDR6, which affects all current MPC 834x processors, lists changes
required to maintain compatibility with various types of DDR memory. This
patch implements those changes.
Signed-off-by: Timur Tabi <timur@freescale.com>
Incorporated the common unified variable names and the changes in preparation
for releasing mpc8360 patches.
Signed-off-by: Dave Liu <daveliu@freescale.com>