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![Dave Liu](/assets/img/avatar_default.png)
The 834x rev1.x silicon has one CPU5 errata. The issue is when the data cache locked with HID0[DLOCK], the dcbz instruction looks like no-op inst. The right behavior of the data cache is when the data cache Locked with HID0[DLOCK], the dcbz instruction allocates new tags in cache. The 834x rev3.0 and later and 8360 have not this bug inside. So, when 834x rev3.0/8360 are working with ECC, the dcbz instruction will corrupt the stack in cache, the processor will checkstop reset. However, the 834x rev1.x can work with ECC with these code, because the sillicon has this cache bug. The dcbz will not corrupt the stack in cache. Really, it is the fault code running on fault sillicon. This patch fix the incorrect dcbz operation. Instead of CPU FP writing to initialise the ECC. CHANGELOG: * Fix the incorrect dcbz operation instead of CPU FP writing to initialise the ECC memory. Otherwise, it will corrupt the stack in cache, The processor will checkstop reset. Signed-off-by: Dave Liu <daveliu@freescale.com>
639 lines
18 KiB
C
639 lines
18 KiB
C
/*
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* (C) Copyright 2006 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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* 20060601: Dave Liu (daveliu@freescale.com)
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* DDR ECC support
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* unify variable names for 83xx
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* code cleanup
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <spd.h>
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#include <asm/mmu.h>
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#include <spd_sdram.h>
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#ifdef CONFIG_SPD_EEPROM
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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extern void dma_init(void);
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extern uint dma_check(void);
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extern int dma_xfer(void *dest, uint count, void *src);
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#endif
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#ifndef CFG_READ_SPD
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#define CFG_READ_SPD i2c_read
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#endif
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/*
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* Convert picoseconds into clock cycles (rounding up if needed).
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*/
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extern ulong get_ddr_clk(ulong dummy);
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int
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picos_to_clk(int picos)
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{
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unsigned int ddr_bus_clk;
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int clks;
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ddr_bus_clk = get_ddr_clk(0) >> 1;
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clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
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if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) {
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clks++;
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}
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return clks;
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}
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unsigned int banksize(unsigned char row_dens)
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{
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return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
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}
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int read_spd(uint addr)
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{
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return ((int) addr);
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}
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#undef SPD_DEBUG
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#ifdef SPD_DEBUG
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static void spd_debug(spd_eeprom_t *spd)
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{
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printf ("\nDIMM type: %-18.18s\n", spd->mpart);
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printf ("SPD size: %d\n", spd->info_size);
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printf ("EEPROM size: %d\n", 1 << spd->chip_size);
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printf ("Memory type: %d\n", spd->mem_type);
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printf ("Row addr: %d\n", spd->nrow_addr);
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printf ("Column addr: %d\n", spd->ncol_addr);
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printf ("# of rows: %d\n", spd->nrows);
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printf ("Row density: %d\n", spd->row_dens);
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printf ("# of banks: %d\n", spd->nbanks);
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printf ("Data width: %d\n",
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256 * spd->dataw_msb + spd->dataw_lsb);
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printf ("Chip width: %d\n", spd->primw);
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printf ("Refresh rate: %02X\n", spd->refresh);
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printf ("CAS latencies: %02X\n", spd->cas_lat);
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printf ("Write latencies: %02X\n", spd->write_lat);
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printf ("tRP: %d\n", spd->trp);
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printf ("tRCD: %d\n", spd->trcd);
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printf ("\n");
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}
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#endif /* SPD_DEBUG */
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long int spd_sdram()
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
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volatile ddr83xx_t *ddr = &immap->ddr;
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volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
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spd_eeprom_t spd;
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unsigned int memsize;
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unsigned int law_size;
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unsigned char caslat, caslat_ctrl;
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unsigned char burstlen;
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unsigned int max_bus_clk;
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unsigned int max_data_rate, effective_data_rate;
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unsigned int ddrc_clk;
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unsigned int refresh_clk;
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unsigned sdram_cfg;
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unsigned int ddrc_ecc_enable;
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/* Read SPD parameters with I2C */
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CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
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#ifdef SPD_DEBUG
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spd_debug(&spd);
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#endif
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/* Check the memory type */
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if (spd.mem_type != SPD_MEMTYPE_DDR) {
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printf("DDR: Module mem type is %02X\n", spd.mem_type);
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return 0;
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}
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/* Check the number of physical bank */
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if (spd.nrows > 2) {
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printf("DDR: The number of physical bank is %02X\n", spd.nrows);
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return 0;
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}
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/* Check if the number of row of the module is in the range of DDRC */
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if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
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printf("DDR: Row number is out of range of DDRC, row=%02X\n",
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spd.nrow_addr);
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return 0;
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}
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/* Check if the number of col of the module is in the range of DDRC */
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if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
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printf("DDR: Col number is out of range of DDRC, col=%02X\n",
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spd.ncol_addr);
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return 0;
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}
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/* Setup DDR chip select register */
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#ifdef CFG_83XX_DDR_USES_CS0
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ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
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ddr->cs_config[0] = ( 1 << 31
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| (spd.nrow_addr - 12) << 8
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| (spd.ncol_addr - 8) );
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debug("\n");
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debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
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debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
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if (spd.nrows == 2) {
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ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
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| ((banksize(spd.row_dens) >> 23) - 1) );
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ddr->cs_config[1] = ( 1<<31
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| (spd.nrow_addr-12) << 8
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| (spd.ncol_addr-8) );
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debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
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debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
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}
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#else
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ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
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ddr->cs_config[2] = ( 1 << 31
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| (spd.nrow_addr - 12) << 8
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| (spd.ncol_addr - 8) );
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debug("\n");
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debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
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debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
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if (spd.nrows == 2) {
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ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
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| ((banksize(spd.row_dens) >> 23) - 1) );
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ddr->cs_config[3] = ( 1<<31
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| (spd.nrow_addr-12) << 8
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| (spd.ncol_addr-8) );
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debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
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debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
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}
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#endif
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if (spd.mem_type != 0x07) {
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puts("No DDR module found!\n");
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return 0;
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}
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/*
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* Figure out memory size in Megabytes.
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*/
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memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
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/*
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* First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
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*/
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law_size = 19 + __ilog2(memsize);
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/*
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* Set up LAWBAR for all of DDR.
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*/
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ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
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debug("DDR:bar=0x%08x\n", ecm->bar);
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debug("DDR:ar=0x%08x\n", ecm->ar);
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/*
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* Find the largest CAS by locating the highest 1 bit
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* in the spd.cas_lat field. Translate it to a DDR
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* controller field value:
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*
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* CAS Lat DDR I Ctrl
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* Clocks SPD Bit Value
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* -------+--------+---------
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* 1.0 0 001
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* 1.5 1 010
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* 2.0 2 011
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* 2.5 3 100
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* 3.0 4 101
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* 3.5 5 110
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* 4.0 6 111
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*/
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caslat = __ilog2(spd.cas_lat);
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if (caslat > 6 ) {
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printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n",
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spd.cas_lat);
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return 0;
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}
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max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
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+ (spd.clk_cycle & 0x0f));
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max_data_rate = max_bus_clk * 2;
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debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
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ddrc_clk = get_ddr_clk(0) / 1000000;
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if (max_data_rate >= 390) { /* it is DDR 400 */
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if (ddrc_clk <= 410 && ddrc_clk > 350) {
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/* DDR controller clk at 350~410 */
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effective_data_rate = 400; /* 5ns */
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caslat = caslat;
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} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
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/* DDR controller clk at 280~350 */
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effective_data_rate = 333; /* 6ns */
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if (spd.clk_cycle2 == 0x60) {
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caslat = caslat - 1;
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} else {
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caslat = caslat;
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}
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} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
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/* DDR controller clk at 230~280 */
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effective_data_rate = 266; /* 7.5ns */
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if (spd.clk_cycle3 == 0x75) {
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caslat = caslat - 2;
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} else if (spd.clk_cycle2 == 0x60) {
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caslat = caslat - 1;
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} else {
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caslat = caslat;
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}
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} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
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/* DDR controller clk at 90~230 */
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effective_data_rate = 200; /* 10ns */
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if (spd.clk_cycle3 == 0x75) {
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caslat = caslat - 2;
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} else if (spd.clk_cycle2 == 0x60) {
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caslat = caslat - 1;
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} else {
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caslat = caslat;
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}
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}
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} else if (max_data_rate >= 323) { /* it is DDR 333 */
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if (ddrc_clk <= 350 && ddrc_clk > 280) {
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/* DDR controller clk at 280~350 */
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effective_data_rate = 333; /* 6ns */
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caslat = caslat;
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} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
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/* DDR controller clk at 230~280 */
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effective_data_rate = 266; /* 7.5ns */
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if (spd.clk_cycle2 == 0x75) {
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caslat = caslat - 1;
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} else {
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caslat = caslat;
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}
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} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
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/* DDR controller clk at 90~230 */
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effective_data_rate = 200; /* 10ns */
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if (spd.clk_cycle3 == 0xa0) {
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caslat = caslat - 2;
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} else if (spd.clk_cycle2 == 0x75) {
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caslat = caslat - 1;
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} else {
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caslat = caslat;
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}
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}
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} else if (max_data_rate >= 256) { /* it is DDR 266 */
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if (ddrc_clk <= 350 && ddrc_clk > 280) {
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/* DDR controller clk at 280~350 */
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printf("DDR: DDR controller freq is more than "
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"max data rate of the module\n");
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return 0;
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} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
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/* DDR controller clk at 230~280 */
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effective_data_rate = 266; /* 7.5ns */
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caslat = caslat;
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} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
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/* DDR controller clk at 90~230 */
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effective_data_rate = 200; /* 10ns */
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if (spd.clk_cycle2 == 0xa0) {
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caslat = caslat - 1;
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}
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}
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} else if (max_data_rate >= 190) { /* it is DDR 200 */
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if (ddrc_clk <= 350 && ddrc_clk > 230) {
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/* DDR controller clk at 230~350 */
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printf("DDR: DDR controller freq is more than "
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"max data rate of the module\n");
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return 0;
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} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
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/* DDR controller clk at 90~230 */
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effective_data_rate = 200; /* 10ns */
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caslat = caslat;
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}
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}
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debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
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debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
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/*
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* Errata DDR6 work around: input enable 2 cycles earlier.
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* including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
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*/
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if (caslat == 2) {
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ddr->debug_reg = 0x201c0000; /* CL=2 */
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} else if (caslat == 3) {
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ddr->debug_reg = 0x202c0000; /* CL=2.5 */
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} else if (caslat == 4) {
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ddr->debug_reg = 0x202c0000; /* CL=3.0 */
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}
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__asm__ __volatile__ ("sync");
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debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
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/*
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* note: caslat must also be programmed into ddr->sdram_mode
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* register.
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*
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* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
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* use conservative value here.
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*/
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caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
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ddr->timing_cfg_1 =
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(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
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((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
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((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
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((caslat_ctrl & 0x07) << 16 ) |
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(((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
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( 0x300 ) |
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((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
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ddr->timing_cfg_2 = 0x00000800;
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debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
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debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
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/* Setup init value, but not enable */
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ddr->sdram_cfg = 0x42000000;
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/* Check DIMM data bus width */
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if (spd.dataw_lsb == 0x20) {
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burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
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printf("\n DDR DIMM: data bus width is 32 bit");
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} else {
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burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
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printf("\n DDR DIMM: data bus width is 64 bit");
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}
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/* Is this an ECC DDR chip? */
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if (spd.config == 0x02) {
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printf(" with ECC\n");
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} else {
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printf(" without ECC\n");
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}
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/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
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Burst type is sequential
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*/
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switch (caslat) {
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case 1:
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ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
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break;
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case 2:
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ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
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break;
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case 3:
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ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
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break;
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case 4:
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ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
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break;
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default:
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printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
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return 0;
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}
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debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
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switch (spd.refresh) {
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case 0x00:
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case 0x80:
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refresh_clk = picos_to_clk(15625000);
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break;
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case 0x01:
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case 0x81:
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refresh_clk = picos_to_clk(3900000);
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break;
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case 0x02:
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case 0x82:
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refresh_clk = picos_to_clk(7800000);
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break;
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case 0x03:
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case 0x83:
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refresh_clk = picos_to_clk(31300000);
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break;
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case 0x04:
|
|
case 0x84:
|
|
refresh_clk = picos_to_clk(62500000);
|
|
break;
|
|
case 0x05:
|
|
case 0x85:
|
|
refresh_clk = picos_to_clk(125000000);
|
|
break;
|
|
default:
|
|
refresh_clk = 0x512;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Set BSTOPRE to 0x100 for page mode
|
|
* If auto-charge is used, set BSTOPRE = 0
|
|
*/
|
|
ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
|
|
debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
|
|
|
|
/* SS_EN = 0, source synchronous disable
|
|
* CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
|
|
*/
|
|
ddr->sdram_clk_cntl = 0x00000000;
|
|
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
|
|
|
|
asm("sync;isync");
|
|
|
|
udelay(600);
|
|
|
|
/*
|
|
* Figure out the settings for the sdram_cfg register. Build up
|
|
* the value in 'sdram_cfg' before writing since the write into
|
|
* the register will actually enable the memory controller, and all
|
|
* settings must be done before enabling.
|
|
*
|
|
* sdram_cfg[0] = 1 (ddr sdram logic enable)
|
|
* sdram_cfg[1] = 1 (self-refresh-enable)
|
|
* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
|
|
* sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
|
|
* sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
|
|
*/
|
|
sdram_cfg = 0xC2000000;
|
|
|
|
/* sdram_cfg[3] = RD_EN - registered DIMM enable */
|
|
if (spd.mod_attr & 0x02) {
|
|
sdram_cfg |= 0x10000000;
|
|
}
|
|
|
|
/* The DIMM is 32bit width */
|
|
if (spd.dataw_lsb == 0x20) {
|
|
sdram_cfg |= 0x000C0000;
|
|
}
|
|
ddrc_ecc_enable = 0;
|
|
|
|
#if defined(CONFIG_DDR_ECC)
|
|
/* Enable ECC with sdram_cfg[2] */
|
|
if (spd.config == 0x02) {
|
|
sdram_cfg |= 0x20000000;
|
|
ddrc_ecc_enable = 1;
|
|
/* disable error detection */
|
|
ddr->err_disable = ~ECC_ERROR_ENABLE;
|
|
/* set single bit error threshold to maximum value,
|
|
* reset counter to zero */
|
|
ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
|
|
(0 << ECC_ERROR_MAN_SBEC_SHIFT);
|
|
}
|
|
|
|
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
|
|
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
|
|
#endif
|
|
printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
|
|
|
|
#if defined(CONFIG_DDR_2T_TIMING)
|
|
/*
|
|
* Enable 2T timing by setting sdram_cfg[16].
|
|
*/
|
|
sdram_cfg |= SDRAM_CFG_2T_EN;
|
|
#endif
|
|
/* Enable controller, and GO! */
|
|
ddr->sdram_cfg = sdram_cfg;
|
|
asm("sync;isync");
|
|
udelay(500);
|
|
|
|
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
|
|
return memsize; /*in MBytes*/
|
|
}
|
|
#endif /* CONFIG_SPD_EEPROM */
|
|
|
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
|
|
/*
|
|
* Use timebase counter, get_timer() is not availabe
|
|
* at this point of initialization yet.
|
|
*/
|
|
static __inline__ unsigned long get_tbms (void)
|
|
{
|
|
unsigned long tbl;
|
|
unsigned long tbu1, tbu2;
|
|
unsigned long ms;
|
|
unsigned long long tmp;
|
|
|
|
ulong tbclk = get_tbclk();
|
|
|
|
/* get the timebase ticks */
|
|
do {
|
|
asm volatile ("mftbu %0":"=r" (tbu1):);
|
|
asm volatile ("mftb %0":"=r" (tbl):);
|
|
asm volatile ("mftbu %0":"=r" (tbu2):);
|
|
} while (tbu1 != tbu2);
|
|
|
|
/* convert ticks to ms */
|
|
tmp = (unsigned long long)(tbu1);
|
|
tmp = (tmp << 32);
|
|
tmp += (unsigned long long)(tbl);
|
|
ms = tmp/(tbclk/1000);
|
|
|
|
return ms;
|
|
}
|
|
|
|
/*
|
|
* Initialize all of memory for ECC, then enable errors.
|
|
*/
|
|
/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
|
|
void ddr_enable_ecc(unsigned int dram_size)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
|
|
volatile ddr83xx_t *ddr= &immap->ddr;
|
|
unsigned long t_start, t_end;
|
|
register u64 *p;
|
|
register uint size;
|
|
unsigned int pattern[2];
|
|
#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
|
|
uint i;
|
|
#endif
|
|
icache_enable();
|
|
t_start = get_tbms();
|
|
pattern[0] = 0xdeadbeef;
|
|
pattern[1] = 0xdeadbeef;
|
|
|
|
#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
|
|
debug("ddr init: CPU FP write method\n");
|
|
size = dram_size;
|
|
for (p = 0; p < (u64*)(size); p++) {
|
|
ppcDWstore((u32*)p, pattern);
|
|
}
|
|
__asm__ __volatile__ ("sync");
|
|
#else
|
|
debug("ddr init: DMA method\n");
|
|
size = 0x2000;
|
|
for (p = 0; p < (u64*)(size); p++) {
|
|
ppcDWstore((u32*)p, pattern);
|
|
}
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* Initialise DMA for direct transfer */
|
|
dma_init();
|
|
/* Start DMA to transfer */
|
|
dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
|
|
dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
|
|
dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
|
|
dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
|
|
dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
|
|
dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
|
|
dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
|
|
dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
|
|
dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
|
|
dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
|
|
|
|
for (i = 1; i < dram_size / 0x800000; i++) {
|
|
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
|
|
}
|
|
#endif
|
|
|
|
t_end = get_tbms();
|
|
icache_disable();
|
|
|
|
debug("\nREADY!!\n");
|
|
debug("ddr init duration: %ld ms\n", t_end - t_start);
|
|
|
|
/* Clear All ECC Errors */
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_MME;
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_MBE;
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_SBE;
|
|
if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
|
|
ddr->err_detect |= ECC_ERROR_DETECT_MSE;
|
|
|
|
/* Disable ECC-Interrupts */
|
|
ddr->err_int_en &= ECC_ERR_INT_DISABLE;
|
|
|
|
/* Enable errors for ECC */
|
|
ddr->err_disable &= ECC_ERROR_ENABLE;
|
|
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
}
|
|
#endif /* CONFIG_DDR_ECC */
|