Commit Graph

60256 Commits

Author SHA1 Message Date
Joris Offouga
f730fdf98b pico-imx7d: fix splash logo drawing
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
2019-10-08 16:36:37 +02:00
Stefano Babic
d714a75fd4 imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-10-08 16:36:37 +02:00
Igor Opaniuk
c115cd154c pinctrl: nxp: DM_FLAG_PRE_RELOC by default
For NXP SoCs we have to set pinmux configuration ASAP (ideally
before relocation) to get serial console working. Without this we miss
almost the half of output (U-boot version, CPU defails, Reset cause,
DRAM details etc.).

To achieve this we need to force appropriate pinctrl drivers to get
probed before relocation.

Fixes: cd69e8ef9b ("colibri-imx6ull: migrate pinctrl and regulators to dtb/dm")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-08 16:36:37 +02:00
Parthiban Nallathambi
39fd054fee configs: move CONFIG_SPL_TEXT_BASE to Kconfig
CONFIG_SPL_TEXT_BASE is moved to common/spl/Kconfig, update
pcl063_ull defconfig.

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
2019-10-08 16:36:37 +02:00
Saravanan Sekar
a7031d9f54 imx: variscite: Fix regression of SPL and U-boot booting
1. Commit 3a7c45f6a7 ("simple-bus: add DM_FLAG_PRE_RELOC flag to
simple-bus driver") causes some i.MX boards that were converted
to DM, such as warp7, to fail to boot.

As explained by Lukas Auer:

"With the patch, U-Boot probes the drivers for devices under simple-bus
device tree nodes in the pre-relocation device model. The default value
of CONFIG_SYS_MALLOC_F_LEN (0x4000) leaves U-Boot with not enough memory to
do this, causing it to hang."

Fix this problem by providing a convenient default value for
CONFIG_SYS_MALLOC_F_LEN.

2. CONFIG_SPL_TEXT_BASE was moved to Kconfig, so added in defconfig
"configs: move CONFIG_SPL_TEXT_BASE to Kconfig"
(sha1: f89d6133ee)

Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Adam Ford
7cf388fa69 ARM: imx6q_logic: Enable DM_SERIAL
In order to call preloader_console_init from board_init_f when
DM_SERIAL is enabled, it neesd to call spl_early_init() to get early access
to DM and device tree.

This patch calls spl_early_init just before preloader_console_init()
and enables DM_SERIAL and SPL_DM_SERIAL.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-10-08 16:36:37 +02:00
Adam Ford
a3ecce373a ARM: imx6qlogic: Cleanup board_init_f
Per the workflow found in crt0.S, we don't need to clear BSS in
board_init_f nor do we need to call board_init_r since that will be
done for us from main when we return from board_init_f.

This patch removes the unneeded function calls from board_init_f.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-10-08 16:36:37 +02:00
Breno Matheus Lima
80be404a25 mx6ulevk: Include SDP boot instructions in README
Add instructions on how to boot mx6ul_14x14_evk_defconfig target
using the Serial Download Protocol.

Add examples from uuu and imx_usb_loader tools.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-10-08 16:36:37 +02:00
Jacky Bai
69b8e50975 ddr: imx8m: Fix the ddr init hang on imx8mq
On, i.MX8MQ, the PLL config must be done when ddrmix
isolation is released. So move the dram pll init after
iso config done. For other i.MX8M SOC, either init pll
before or after isolation is ok.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Jacky Bai
825ab6b406 driver: ddr: Refine the ddr init driver on imx8m
Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Bai Ping
7b14cc991b imx8mq: Update the ddrc QoS setting for B1 chip
Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
2019-10-08 16:36:37 +02:00
Ye Li
ca729cd16c ddr: imx8m: Fix ddr4 driver build issue
Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Ye Li
9699fb4de5 spi: fsl_qspi: Add support for QSPI on iMX7ULP
Add the compatible string and driver data for iMX7ULP platform

Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08 16:36:37 +02:00
Ye Li
ce7575a86d spi: fsl_qspi: Update to use driver data
Add the driver data for each compatible string. So we can remove the
SOC config and use driver data instead.

Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08 16:36:37 +02:00
Ye Li
b866b9278a spi: fsl_qspi: Update write data size for page program LUT
The write data size can be overwritten by writing to the IDATSZ
field of IPCR register. Since the driver always updates the IDATSZ
in page program operation. Set the LUT data size to 0 to align
the codes with iMX.

Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08 16:36:37 +02:00
Ye Li
7949576664 spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms
On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller
is updated to have TDH field in FLSHCR register. According to reference
manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX
DDR delay logic won't be enabled.

Another issue in DDR mode is the MCR register will be overwritten in
every read/write/erase operation. This causes DDR_EN been cleared while
TDH=1, then no clk2x output for TX data shift and all operations will
fail.

Signed-off-by: Ye Li <ye.li@nxp.com>
2019-10-08 16:36:37 +02:00
Parthiban Nallathambi
4ee0ff1268 imx: nandbcb: include long help only when enabled
conditionally include long help text when enabled

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Parthiban Nallathambi
921bb8641d imx: initialize fec only when enabled
board early initialize fec ethernet controller pinmux
only when FEC is enabled

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Parthiban Nallathambi
84d5e72ffb imx: remove board specific boot order from spl
boot order was added to handle both SD and eMMC. But commit
14d319b1 introduced to handle both eMMC and SD globally.

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Parthiban Nallathambi
a919b6ba37 imx: pcl063: add nand boot support
Booting from NAND needs nandbcb and nand boot device selection

Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:37 +02:00
Igor Opaniuk
d73c520327 apalis_imx6: use distroboot by default
Use distro_bootcmd as default bootcmd instead of legacy wrappers.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-08 16:36:36 +02:00
Igor Opaniuk
848ba639dc colibri_imx6/imx7/imx8x: use distroboot by default
Use distro_bootcmd as defauult bootcmd instead of legacy wrappers.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-10-08 16:36:36 +02:00
Peng Fan
4d81755272 misc: imx8: add more scfw api
Add more scfw api for clk/partition/seco usage
The api will be used by ccf/partition/secure boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
3bc4f1df03 spl: nor: support loading i.MX container format file
i.MX8 only support AHAB secure boot with Container format image,
we could not use FIT to support secure boot, so introduce container
support to let SPL could load container images.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
d9bd2f4a4e spl: spi: support loading i.MX container format file
i.MX8 only support AHAB secure boot with Container format image,
we could not use FIT to support secure boot, so introduce container
support to let SPL could load container images.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
00e180cc51 spl: nand: support loading i.MX container format file
i.MX8 only support AHAB secure boot with Container format image,
we could not use FIT to support secure boot, so introduce container
support to let SPL could load container images.

Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
62f0bfc016 imx8: update README
After u-boot.cnt is padded to flash.bin automatically by script,
no need to burn the image mannually, so drop the step.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
d1c07785fd imx8: Add support to get container image set size
To avoid hardcoded offset when adding u-boot.cnt to flash.bin, we use
flexible offset which is calculated based on the size of the container
image generated int the first stage. And pad u-boot.cnt at 1KB
alignment.

So add code to get the offset when SPL loading u-boot.cnt.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
2c79229c02 spl: nand: Introduce spl_nand_get_uboot_raw_page
Introduce weak spl_nand_get_uboot_raw_page, then platform could
have their own implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2019-10-08 16:36:36 +02:00
Peng Fan
07d900af76 spl: nor: introduce spl_nor_get_uboot_base
Introduce weak spl_nor_get_uboot_base, then platform have their own
implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2019-10-08 16:36:36 +02:00
Peng Fan
ec64933094 spl: spi: introduce spl_spi_get_uboot_offs
Introduce a weak function spl_spi_get_uboot_offs, then
platform could have their own implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2019-10-08 16:36:36 +02:00
Peng Fan
30ecc9c323 spl: mmc: introduce spl_mmc_get_uboot_raw_sector
Introduce a weak function spl_mmc_get_uboot_raw_sector, then platform
could have their own implementation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2019-10-08 16:36:36 +02:00
Peng Fan
9b15ce9193 imx: Add i.MX8MM EVK board support.
Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
d68d73df17 arm: dts: add i.MX8MM pin func
Import i.MX8MM pin func from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
2f1723132e arm: dts: import i.MX8MM dtsi
Import i.MX8MM dtsi from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
e663c703b1 imx8m: soc: probe clock device in arch_cpu_init_dm
Because we need to get cpu freq in print_cpuinfo at very early stage,
so we need to make sure the ccm be probed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
e89d211f30 imx: mmc_env: update runtime SD/MMC boot env device
When DM_MMC enabled, the USDHC index in U-Boot is the USDHC port.
To directly return devno, we could avoid add board specific code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
5f24d0cb9c imx8m: add clk support for i.MX8MM
Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
8838cdf10d imx8m: restructure clock.h
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
2005916f54 imx8m: rename clock to clock_imx8mq
i.MX8MQ and i.MX8MM has totally different pll design, so
rename clock to clock_imx8mq.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
d2041725e8 imx8m: restrict reset_cpu
Make reset_cpu only visible when CONFIG_SYSRESET not defined
or CONFIG_SPL_BUILD.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
0528ba0e1c imx8m: soc: enable SCTR clock before timer init
To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Ye Li
b3cf0a8f03 imx8m: Configure trustzone region 0 for non-secure access
Set trustzone region 0 to allow both non-secure and secure access
when trust zone is enabled. We found USB controller fails to access
DDR if the default region 0 is secure access only.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
dbb2b7e508 imx8m: set BYPASS ID SWAP to avoid AXI bus errors
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
59efa6b52b imx8m: Fix MMU table issue for OPTEE memory
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
1c7cba9fa7 imx: add i.MX8MM PE property
i.MX8MM does not have LVTTL, it has a PE property

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
e246b7ad74 imx8m: add pin header for i.MX8MM
Add pin header file for i.MX8MM

To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
78db9a5463 imx: add get_cpu_rev support for i.MX8MM
There are several variants based on i.MX8MM, add the support in
get_cpu_rev

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
20ebb4fa75 imx8m: update imx-regs for i.MX8MM
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and register layout change.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00
Peng Fan
4800df0cb0 imx8m: imx-regs: drop unused register definitions
Drop unused register definitions and structures for i.MX8MQ

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-08 16:36:36 +02:00