MIPSfpga is an FPGA based dev platform.
In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks
The FPGA dev board used is the Nexys4DDR board by Digilent.
For more information, check the Readme file in board/imgtec/xilfpga
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Mostly the same as the Kernel upstream device tree file except for
- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-frequency passed directly in the node
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config
There are two boards, MIP405 and MIP405T that have a few differences.
Start by checking for CONFIG_TARGET_MIP405. Then introduce
CONFIG_TARGET_MIP405T and use that not CONFIG_MIP405T. Next, convert
also convert the usage of CONFIG_ISO_STRING to be based on Kconfig.
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the config IDENT_STRING to Kconfig and migrate all boards
[sivadur: Migrate zynq boards]
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[trini: Update configs, add some default to sunxi Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
Import the latest version from the Diag software.
- Support LD21 SoC (including DDR chips in the package)
- Per-board granule adjustment for both reference and TV boards
- Misc cleanups
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper. Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper. Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper. Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is the last code in the mach-uniphier/pinctrl/ directory.
Push the remaining code out to delete the directory entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This will be needed for setting up the System Bus pin-mux via the
LD11/LD20 pinctrl driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers. Use them by
calling pinctrl_generic_set_state() directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now all UniPhier SoCs support a pinctrl driver. Select (SPL_)PINCTRL
since it is mandatory even for base use.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb
and one usb OTG connector.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Linux kernel musb driver expects VBUS to be off while initializing
musb. Having it on results in a repeating string of warnings, followed
by an unusable peripheral. The peripheral is only usable after
physically removing the OTG adapter, letting musb reset its state.
This partially reverts commit c9f8947e66 ("sunxi: usb-phy: Never
power off the usb ports")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
There are a few options which use lower case. We should use upper case for
all CONFIG options.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.
Note that quite a few boards defined this options but do not appear to
actually use SPL:
BSC9132QDS_NOR_DDRCLK100_SECURE
BSC9132QDS_NOR_DDRCLK133_SECURE
BSC9132QDS_SDCARD_DDRCLK100_SECURE
BSC9132QDS_SDCARD_DDRCLK133_SECURE
BSC9132QDS_SPIFLASH_DDRCLK100_SECURE
BSC9132QDS_SPIFLASH_DDRCLK133_SECURE
C29XPCIE_NOR_SECBOOT
P1010RDB-PA_36BIT_NAND_SECBOOT
P1010RDB-PA_36BIT_SPIFLASH_SECBOOT
P1010RDB-PA_NAND_SECBOOT
P1010RDB-PA_NOR_SECBOOT
P1010RDB-PB_36BIT_NOR_SECBOOT
P1010RDB-PB_36BIT_SPIFLASH_SECBOOT
P1010RDB-PB_NAND_SECBOOT
P1010RDB-PB_NOR_SECBOOT
P3041DS_SECURE_BOOT
P4080DS_SECURE_BOOT
P5020DS_NAND_SECURE_BOOT
P5040DS_SECURE_BOOT
T1023RDB_SECURE_BOOT
T1024QDS_DDR4_SECURE_BOOT
T1024QDS_SECURE_BOOT
T1024RDB_SECURE_BOOT
T1040RDB_SECURE_BOOT
T1042D4RDB_SECURE_BOOT
T1042RDB_SECURE_BOOT
T2080QDS_SECURE_BOOT
T2080RDB_SECURE_BOOT
T4160QDS_SECURE_BOOT
T4240QDS_SECURE_BOOT
ls1021aqds_nor_SECURE_BOOT
ls1021atwr_nor_SECURE_BOOT
ls1043ardb_SECURE_BOOT
For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since
they apparently don't have an SPL, this should not matter.
Signed-off-by: Simon Glass <sjg@chromium.org>
The secure boot header files incorrectly define SPL options only if
CONFIG_SPL_BUILD is defined. This means that the options are only enabled
in an SPL build, and not with a normal 'make xxx_defconfig'. This means
that moveconfig.py cannot work, since it sees the options as disabled even
when they may be manually enabled in an SPL build.
Fix this by changing the order.
Signed-off-by: Simon Glass <sjg@chromium.org>
Unfortunately, this SoC needs per-board adjustment between clock
and address/command lines. This flag will be passed to the DRAM
init function and used for compensating the difference of DRAM
timing parameters.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
With newer ARC tools old way of CPU specification gets obsolete,
so we're switching to newer and more common way of setting "-mcpu".
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
LS1046AQDS Specification:
-------------------------
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two XFI 10G ports
* Two SGMII ports
* Two RGMII ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1046ARDB Specification:
-------------------------
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 512 Mbyte NAND flash
* Two 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
* On-board 4G eMMC
Ethernet:
* Two XFI 10G ports
* Two SGMII ports
* Two RGMII ports
PCIe:
* PCIe1 (SerDes2 Lane0) to miniPCIe slot
* PCIe2 (SerDes2 Lane1) to x2 PCIe slot
* PCIe3 (SerDes2 Lane2) to x4 PCIe slot
SATA:
* SerDes2 Lane3 to SATA port
USB 3.0: one super speed USB 3.0 type A port
one Micro-AB port
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly. Clearing BSS and calling board_init_r() will be done in
crt0_64.S.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The EPU Finite State Machie (FSM) is used in both the last stage of
system suspend and the earliest stage of system resume.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds definitions of all the regesters necessary for
system sleep.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Currently, the UniPhier platform calls several init functions in the
following order:
[1] spl_board_init()
[2] board_early_init_f()
[3] board_init()
[4] board_early_init_r()
[5] board_late_init()
The serial console is not ready at the point of [2], so we want to
avoid using [2] from the view point of debuggability. Fortunately,
all of the initialization in [2] can be delayed until [3]. I see no
good reason to split into [3] and [4]. So, merge [2] through [4].
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We can use checkboard() stub to show additional board information,
so misc_init_f() should not be used for this purpose.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is the state-of-the-art MMC driver implementation.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver has not been converted to Driver Model, and it is an
obstacle to migrate other block device drivers. Remove it for now.
The UniPhier SoCs already use a DM-based EHCI driver, so now
ARCH_UNIPHIER can select DM_USB.
These two changes must be done atomically because removing the
legacy driver causes a build error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
ARCH_UNIPHIER is having more and more select:s. Sort them in case
a select is accidentally duplicated.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
We are supposed to not add config entries with only "default y"
in board/SoC Kconfig files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Move this option to Kconfig and set its default value to 4; this
increases the number of supported CPUs for some boards.
It consumes 1KB memory per CPU for PSCI stack, but it should not
be a big deal, given the amount of memory used for the modern OSes.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select. Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_ARMV7_NONSEC is enabled, the linker script requires
CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
SPL_BUILD is not a CONFIG in Kconfig, so !SPL_BUILD is always true.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area. As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow. As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.
Tested on OMAP4 Pandaboard, OMAP3 Beagle xM
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Weber <weber@corscience.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: "B, Ravi" <ravibabu@ti.com>
Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Import DTS files and dt-bindings includes from Linux 4.8-rc1.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
So far we could only tell the gpio framework that a GPIO was mapped as input or
output, not as alternative function.
This patch adds support for determining whether a function is mapped as
alternative.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
With commit ceec08f50b, phy is connected to slave 0, but
changing the phy node was missed, fix it by populating the
phy node to proper cpsw slave node.
Fixes: ceec08f50b ("ARM: dts: dra72-evm: Add mode-gpios entry for mac node")
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Vignesh R <vigneshr@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus,
with 2G RAM and an external gbit ethernet phy.
The dts file is identical to the one submitted to the upstream kernel,
except that it has the pending patch to enable the ethernet controller
squashed in, as u-boot already has sun8i-emac support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This adds an emac node to the orangepi-2 dts (not yet merged upstream,
but in u-boot we already have emac support); fixes the alphetically
sorting of nodes in sun8i-h3-orangepi-plus.dts and disables some
usb controllers in sun8i-h3-orangepi-plus.dts which are only used
on the plus2e, as upstream has decided to do a separate dts files
for the plus2e.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The sun8i-emac driver follows an old version of the proposed DT
bindings, where the EMAC clock and EPHY control register range is
listed directly, rather than through a syscon phandle.
Add back the syscon register range to avoid an invalid data access.
We should fix the driver once the Linux kernel bindings have been
finalized.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
A33-OLinuXino is A33 development board designed by Olimex LTD.
It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
headphone and mic jacks, connector for LiPo battery and optional
4GB NAND Flash.
It has two 40-pin headers. One for LCD panel, and one for
additional modules. Also there is CSI/DSI connector.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add a proper dts for the iNet D978 rev2 based A33 tablets.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Colorado TK1 SOM is a small form factor board similar to the
Jetson TK1. The main differences lie in the pinmux, and in that the
PCIe controller is set to use in 4lanes+1lane, rather than 2+2.
The pinmux header here was generated from a spreadsheet provided by
Colorado Engineering using the tegra-pinmux scripts. The spreadsheet
was converted from v09 to v11 by me.
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric
versioning scheme, with version numbers such as 000/100/200/300/400/500.
Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00.
However, that numbering scheme is not easily visible outside of NVIDIA,
and so does not make much sense to use. Convert U-Boot to use the readily
visible numeric scheme.
Also, it turns out that the current A02 DT actually applies to board
versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200
so that all U-Boot builds are named after the first version of the HW they
support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There are lots of warnings when building EFI 64-bit payload.
include/asm-generic/bitops/__fls.h:17:2:
warning: left shift count >= width of type
if (!(word & (~0ul << 32))) {
^
In fact, U-Boot itself as EFI payload is running in 32-bit mode.
So BITS_PER_LONG needs to still be 32, but EFI status codes are
64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG
to bridge those status codes with U-Boot's BITS_PER_LONG.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.
Adjust the ivybridge code to avoid assuming this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a debug() at this point to help figure out what is wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The eMMC on sLD3 is assigned with dedicated pins (only multiplexed
with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The revision of the original support card (rev 3.5, rev 3.6) fits in
the 8 bit width revision register. When it was extended in a weird
way, it was versioned in the format of "3.6.x" (where it should have
been "3.7", of course). What is worse, only the sub-level version
"6.x" was recorded in the 8 bit width register, completely ignoring
the compatibility of the revision register format.
This patch saves madly-versioned support cards by assuming the major
version "3" when the MSB 4 bit of the register is read as "6". With
this, the support card revision that were displayed as "6.10" is now
corrected to "3.6.10".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This supports the system reset via PSCI for ARMv7 SoCs.
Because the system reset is not supported on PSCI 0.1, let's define
CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there
is no CONFIG to enable it in U-Boot for now.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.
The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".
An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed by: Peter Korsgaard <peter@korsgaard.com>
Add a defconfig and dts file for the Empire Electronix M712 tablet, this
is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on
the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV
wifi chip and a DMART06 (1238a4) accelerometer.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Sync dts files with the current (Aug 18th 2016) state of Maxime's
linux/sunxi/for-next repo.
Note this commit also updates configs/MSI_Primo81_defconfig,
adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary
because the tablet does not have a reachable uart so the dts sync
drops its serial0 alias.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a defconfig and dts file for tablets using the generic inet-q972 PCB.
Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host,
micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot,
(mini) power-barrel and an usb wifi module.
This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Ensure appropriate error messages are generated. Previously all errors
indicated that the serdes was already in use. Now appropriate error
messages are given.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The nvidia,bpmp property is left over from an old BPMP I2C binding, and
shouldn't be present. Remove it from the SoC DT file, and update the
I2C driver not to parse it; the value wasn't used for anything any more
anyway.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra SDHCI binding dictates that the reseet name for the Tegra SDHCI
clock be "sdhci" not "sdmmc", and that the clock is accessed by index
rather than by name. Fix the Tegra186 DT and MMC driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra I2C binding dictates that the clock name for the Tegra I2C clock
be "div-clk" not "i2c". Fix the Tegra186 DT and I2C driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no reason to duplicate code for DRA7xx platforms as there
can be Rail grouping. The maximum voltage detection algorithm can still
be run on other platforms with no Rail grouping and does not harm as
it gives the same result.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
gpio_en field is introduced to detect if pmic is controlled by GPIO.
Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms
and remove the #ifndefs.
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The bootz and booti commands rely on common functionality that is found
in common/bootm.c and common/bootm_os.c. They do not however rely on
the rest of cmd/bootm.c to be implemented so split them into their own
files. Have various Makefiles include the required infrastructure for
CONFIG_CMD_BOOT[IZ] as well as CONFIG_CMD_BOOTM. Move the declaration
of 'images' over to common/bootm.c.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
BLANCHE is development board based on R-Car V2H SoC (R8A7792)
This commit supports the following periherals:
- SCIF, Ethernet, QSPI, MMC
Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Salvator-x is an entry level development board based on
R-Car H3 SoC (R8A7795). This commit supports SCIF only.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Renesas R8A7795 is CPU with Cortex-a57.
This supports the basic register definition and GPIO and
framework of PFC.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds support for the BayTrail based theadorable-x86-dfi-bt700
board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard.
The main difference to the DFI baseboard is, that it isn't equipped
with a Super IO chip and uses the internal HS SIO UART (memory mapped
PCI based) as the console UART.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds support for the DFI BayTrail BT700 QSeven SoM installed
on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton
NCT6102D Super IO chip providing the UART as console.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch includes the following changes:
- Remove Designware I2C support from dts as its not used
- Configure SMBus PADs in dts
- Enable I2C commands and I2C support
- Configure SMSC2513 USB hub via SMBus upon startup
- Move environment location to match Minnowmax example
- Enhancement of the default environment
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds support for the SMBus block read/write functionality.
Other protocols like the SMBus quick command need to get added
if this is needed.
This patch also removed the SMBus related defines from the Ivybridge
pch.h header. As they are integrated in this driver and should be
used from here. This change is added in this patch to avoid compile
breakage to keep the source git bisectable.
Tested on a congatec BayTrail board to configure the SMSC2513 USB
hub.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Explicitly enable ILB_SERIRQ function 1 in
cfio_regs_pad_ilb_serirq_PCONF0.
Pad configuration for SERIRQ is not set to enable the SERIRQ function
after a reset though strangely, it is on initial boot.
Rebooting from Linux, reset command in u-boot and even pushing the reset
button on the development board all lead to the SERIRQ function being
disabled (address 0xfed0c560 with value of 0x2003cc80).
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
To support the BayTrail internal SIO HS UART, the internal UART clock
needs to get configured. This patch adds support for this clock
configuration which will be done, if the PCI device(s) are found.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE
if it's undefined. This is needed for the xhci driver to compile.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The K2G EVM from TI has an SD card slot as
well as onboard eMMC for data storage.
Enable support for these.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
K2G SoC from TI has two MMC/SD controllers.
Add device tree data for these.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The 'xtfpga' board is actually a set of FPGA evaluation boards that
can be configured to run an Xtensa processor.
- Avnet Xilinx LX60
- Avnet Xilinx LX110
- Avnet Xilinx LX200
- Xilinx ML605
- Xilinx KC705
These boards share the same components (open-ethernet, ns16550 serial,
lcd display, flash, etc.).
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
DE212 is a general purpose xtensa processor without full MMU.
Core information files are autogenerated from the processor description
and are not meant to be edited.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
DC233C is an xtensa processor with full MMUv3 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
DC232B is an xtensa processor with full MMUv2 capable of running Linux.
Core information files are autogenerated from the processor description
and are not meant to be edited.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.
This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The firmware on TC2 needs to be configured appropriately before booting
in nonsec mode will work as expected, so test for this and fall back to
sec mode if required.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
