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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

Browse Source
This commit is contained in:
Tom Rini 2016-09-18 12:12:04 -04:00
commit 9a6535e05f
86 changed files with 1473 additions and 1180 deletions
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18
arch/arm/Kconfig
View File

@ -855,18 +855,22 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BLK
select CLK_UNIPHIER
select SUPPORT_SPL
select SPL
select OF_CONTROL
select SPL_OF_CONTROL
select OF_LIBFDT
select DM
select SPL_DM
select DM_GPIO
select DM_SERIAL
select DM_I2C
select DM_MMC
select DM_SERIAL
select DM_USB
select OF_CONTROL
select OF_LIBFDT
select PINCTRL
select SPL
select SPL_DM
select SPL_OF_CONTROL
select SPL_PINCTRL
select SUPPORT_SPL
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)

4
arch/arm/dts/uniphier-ph1-ld11-ref.dts
View File

@ -70,3 +70,7 @@
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
&pinctrl_system_bus {
u-boot,dm-pre-reloc;
};

4
arch/arm/dts/uniphier-ph1-ld20-ref.dts
View File

@ -58,3 +58,7 @@
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
&pinctrl_system_bus {
u-boot,dm-pre-reloc;
};

8
arch/arm/dts/uniphier-ph1-sld3-ref.dts
View File

@ -93,3 +93,11 @@
&emmc {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
&pinctrl_emmc {
u-boot,dm-pre-reloc;
};

35
arch/arm/dts/uniphier-ph1-sld3.dtsi
View File

@ -90,6 +90,8 @@
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart_clk>;
clock-frequency = <36864000>;
};
@ -99,6 +101,8 @@
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart_clk>;
clock-frequency = <36864000>;
};
@ -108,6 +112,8 @@
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&uart_clk>;
clock-frequency = <36864000>;
};
@ -231,6 +237,8 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>;
clock-frequency = <100000>;
};
@ -304,6 +312,9 @@
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio 1>;
bus-width = <8>;
non-removable;
@ -314,6 +325,9 @@
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 76 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio 0>;
bus-width = <4>;
};
@ -323,6 +337,8 @@
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio 3>, <&mio 6>;
};
@ -331,6 +347,8 @@
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio 4>, <&mio 6>;
};
@ -339,6 +357,8 @@
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio 5>, <&mio 6>;
};
@ -347,9 +367,22 @@
status = "disabled";
reg = <0x5a830100 0x100>;
interrupts = <0 83 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&mio 7>, <&mio 6>;
};
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-sld3-pinctrl";
u-boot,dm-pre-reloc;
};
};
aidet@f1830000 {
compatible = "simple-mfd", "syscon";
reg = <0xf1830000 0x200>;
@ -370,3 +403,5 @@
};
};
};
/include/ "uniphier-pinctrl.dtsi"

11
arch/arm/mach-uniphier/Makefile
View File

@ -4,28 +4,25 @@
ifdef CONFIG_SPL_BUILD
obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/
obj-y += init/ bcu/ memconf/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
obj-y += dram_init.o
obj-y += board_common.o
obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-y += board_init.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
obj-y += pinctrl/ clk/
endif
obj-y += boards.o
obj-y += soc_info.o
obj-y += boot-mode/
obj-y += clk/
obj-y += dram/
obj-y += pinctrl-glue.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/

20
arch/arm/mach-uniphier/board_common.c
View File

@ -1,20 +0,0 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "micro-support-card.h"
void uniphier_smp_kick_all_cpus(void);
int board_init(void)
{
led_puts("Uboo");
#ifdef CONFIG_ARM64
uniphier_smp_kick_all_cpus();
#endif
return 0;
}

15
arch/arm/mach-uniphier/board_early_init_r.c
View File

@ -1,15 +0,0 @@
/*
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "micro-support-card.h"
int board_early_init_r(void)
{
support_card_late_init();
return 0;
}

62
arch/arm/mach-uniphier/board_early_init_f.c → arch/arm/mach-uniphier/board_init.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2012-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -10,6 +12,7 @@
#include "init.h"
#include "micro-support-card.h"
#include "sg-regs.h"
#include "soc-info.h"
DECLARE_GLOBAL_DATA_PTR;
@ -45,71 +48,98 @@ static void uniphier_setup_xirq(void)
writel(tmp, 0x55000090);
}
int board_early_init_f(void)
static void uniphier_nand_pin_init(bool cs2)
{
#ifdef CONFIG_NAND_DENALI
if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
pr_err("failed to init NAND pins\n");
#endif
}
int board_init(void)
{
const struct uniphier_board_data *bd;
led_puts("U0");
bd = uniphier_get_board_param();
if (!bd)
return -ENODEV;
switch (uniphier_get_soc_type()) {
#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
case SOC_UNIPHIER_SLD3:
uniphier_sld3_pin_init();
uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_sld3_pll_init();
uniphier_ld4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
case SOC_UNIPHIER_LD4:
uniphier_ld4_pin_init();
uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_ld4_pll_init();
uniphier_ld4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
case SOC_UNIPHIER_PRO4:
uniphier_pro4_pin_init();
uniphier_nand_pin_init(false);
led_puts("U1");
uniphier_pro4_pll_init();
uniphier_pro4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
case SOC_UNIPHIER_SLD8:
uniphier_sld8_pin_init();
uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_ld4_pll_init();
uniphier_ld4_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
case SOC_UNIPHIER_PRO5:
uniphier_pro5_pin_init();
uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_pro5_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
case SOC_UNIPHIER_PXS2:
uniphier_pxs2_pin_init();
uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_pxs2_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
case SOC_UNIPHIER_LD6B:
uniphier_ld6b_pin_init();
uniphier_nand_pin_init(true);
led_puts("U1");
uniphier_pxs2_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
case SOC_UNIPHIER_LD11:
uniphier_ld20_pin_init();
uniphier_nand_pin_init(false);
sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
sg_set_iectrl(149);
sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
sg_set_iectrl(153);
led_puts("U1");
uniphier_ld11_clk_init();
break;
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
case SOC_UNIPHIER_LD20:
uniphier_ld20_pin_init();
uniphier_nand_pin_init(false);
sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
sg_set_iectrl(149);
sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
sg_set_iectrl(153);
led_puts("U1");
uniphier_ld20_pll_init(bd);
uniphier_ld20_clk_init();
cci500_init(2);
break;
@ -122,5 +152,15 @@ int board_early_init_f(void)
led_puts("U2");
support_card_late_init();
led_puts("U3");
#ifdef CONFIG_ARM64
uniphier_smp_kick_all_cpus();
#endif
led_puts("Uboo");
return 0;
}

27
arch/arm/mach-uniphier/boards.c
View File

@ -184,6 +184,27 @@ static const struct uniphier_board_data uniphier_ld11_data = {
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
static const struct uniphier_board_data uniphier_ld20_ref_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0x100000000UL,
.size = 0x40000000,
.width = 32,
},
.flags = UNIPHIER_BD_BOARD_LD20_REF,
};
static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
@ -202,6 +223,7 @@ static const struct uniphier_board_data uniphier_ld20_data = {
.size = 0x40000000,
.width = 32,
},
.flags = UNIPHIER_BD_BOARD_LD20_GLOBAL,
};
static const struct uniphier_board_data uniphier_ld21_data = {
@ -209,7 +231,7 @@ static const struct uniphier_board_data uniphier_ld21_data = {
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
@ -217,7 +239,7 @@ static const struct uniphier_board_data uniphier_ld21_data = {
.size = 0x40000000,
.width = 32,
},
.flags = UNIPHIER_BD_PACKAGE_LD21,
.flags = UNIPHIER_BD_BOARD_LD21_GLOBAL,
};
#endif
@ -255,6 +277,7 @@ static const struct uniphier_board_id uniphier_boards[] = {
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{ "socionext,ph1-ld21", &uniphier_ld21_data, },
{ "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, },
{ "socionext,ph1-ld20", &uniphier_ld20_data, },
#endif
};

28
arch/arm/mach-uniphier/clk/Makefile
View File

@ -2,12 +2,30 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o
else
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
endif
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o

22
arch/arm/mach-uniphier/clk/dpll-ld20.c Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
{
unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
unsigned int dram_freq = bd->dram_freq;
uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
return 0;
}

56
arch/arm/mach-uniphier/clk/dpll-ld4.c Normal file
View File

@ -0,0 +1,56 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#undef DPLL_SSC_RATE_1PER
int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
{
unsigned int dram_freq = bd->dram_freq;
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x000f0000;
switch (dram_freq) {
case 1333:
tmp |= 0x000d0000;
break;
case 1600:
tmp |= 0x000c0000;
break;
default:
pr_err("Unsupported frequency");
return -EINVAL;
}
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~SC_DPLLCTRL_SSC_RATE;
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
return 0;
}

60
arch/arm/mach-uniphier/clk/dpll-pro4.c Normal file
View File

@ -0,0 +1,60 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#undef DPLL_SSC_RATE_1PER
int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
{
unsigned int dram_freq = bd->dram_freq;
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT ( DPLLCTRL.bit[29:20] )
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~(0x000f0000);
switch (dram_freq) {
case 1333:
tmp |= 0x000d0000;
break;
case 1600:
tmp |= 0x000c0000;
break;
default:
pr_err("Unsupported frequency");
return -EINVAL;
}
/*
* Set Moduration rate
* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
*/
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~0x00008000;
#else
tmp |= 0x00008000;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
/* Wait until dpll gets stable */
udelay(500);
return 0;
}

2
arch/arm/mach-uniphier/pll/pll-init-sld3.c → arch/arm/mach-uniphier/clk/dpll-sld3.c
View File

@ -6,7 +6,7 @@
#include "../init.h"
int uniphier_sld3_pll_init(const struct uniphier_board_data *bd)
int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
{
/* add pll init code here */
return 0;

62
arch/arm/mach-uniphier/clk/dpll-sld8.c Normal file
View File

@ -0,0 +1,62 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
{
u32 tmp;
/*
* Set DPLL SSC parameters for DPLLCTRL3
* [23] DIVN_TEST 0x1
* [22:16] DIVN 0x50
* [10] FREFSEL_TEST 0x1
* [9:8] FREFSEL 0x2
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
tmp = readl(SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
writel(tmp, SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
* <-1%> <-2%>
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
writel(tmp, SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
* [31:29] SSC_STEP 0
* [27] SSC_REG_REF 1
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
tmp = readl(SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
writel(tmp, SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
return 0;
}

21
arch/arm/mach-uniphier/clk/dpll-tail.c Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../sc-regs.h"
#include "pll.h"
void uniphier_ld4_dpll_ssc_en(void)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
}

0
arch/arm/mach-uniphier/early-clk/early-clk-ld11.c → arch/arm/mach-uniphier/clk/early-clk-ld11.c
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0
arch/arm/mach-uniphier/early-clk/early-clk-ld20.c → arch/arm/mach-uniphier/clk/early-clk-ld20.c
View File

0
arch/arm/mach-uniphier/early-clk/early-clk-ld4.c → arch/arm/mach-uniphier/clk/early-clk-ld4.c
View File

0
arch/arm/mach-uniphier/early-clk/early-clk-pro5.c → arch/arm/mach-uniphier/clk/early-clk-pro5.c
View File

0
arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c → arch/arm/mach-uniphier/clk/early-clk-pxs2.c
View File

123
arch/arm/mach-uniphier/clk/pll-base-ld20.c Normal file
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@ -0,0 +1,123 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include "pll.h"
/* PLL type: SSC */
#define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
#define SC_PLLCTRL_SSC_EN BIT(31)
#define SC_PLLCTRL2_NRSTDS BIT(28)
#define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
/* PLL type: VPLL27 */
#define SC_VPLL27CTRL_WP BIT(0)
#define SC_VPLL27CTRL3_K_LD BIT(28)
/* PLL type: DSPLL */
#define SC_DSPLLCTRL2_K_LD BIT(28)
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
unsigned int ssc_rate, unsigned int divn)
{
void __iomem *base;
u32 tmp;
base = ioremap(reg_base, SZ_16);
if (!base)
return -ENOMEM;
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
tmp = readl(base); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
tmp |= (487 * freq * ssc_rate / divn / 512) &
SC_PLLCTRL_SSC_DK_MASK;
writel(tmp, base);
tmp = readl(base + 4);
tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
udelay(50);
}
tmp = readl(base + 4); /* SSCPLLCTRL2 */
tmp |= SC_PLLCTRL2_NRSTDS;
writel(tmp, base + 4);
iounmap(base);
return 0;
}
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
{
void __iomem *base;
u32 tmp;
base = ioremap(reg_base, SZ_16);
if (!base)
return -ENOMEM;
mdelay(1);
tmp = readl(base); /* SSCPLLCTRL */
tmp |= SC_PLLCTRL_SSC_EN;
writel(tmp, base);
iounmap(base);
return 0;
}
int uniphier_ld20_vpll27_init(unsigned long reg_base)
{
void __iomem *base;
u32 tmp;
base = ioremap(reg_base, SZ_16);
if (!base)
return -ENOMEM;
tmp = readl(base); /* VPLL27CTRL */
tmp |= SC_VPLL27CTRL_WP; /* write protect off */
writel(tmp, base);
tmp = readl(base + 8); /* VPLL27CTRL3 */
tmp |= SC_VPLL27CTRL3_K_LD;
writel(tmp, base + 8);
tmp = readl(base); /* VPLL27CTRL */
tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
writel(tmp, base);
iounmap(base);
return 0;
}
int uniphier_ld20_dspll_init(unsigned long reg_base)
{
void __iomem *base;
u32 tmp;
base = ioremap(reg_base, SZ_16);
if (!base)
return -ENOMEM;
tmp = readl(base + 8); /* DSPLLCTRL2 */
tmp |= SC_DSPLLCTRL2_K_LD;
writel(tmp, base + 8);
iounmap(base);
return 0;
}

40
arch/arm/mach-uniphier/clk/pll-ld20.c Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
{
unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/* do nothing for SPLL */
uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
mdelay(1);
if (dpll_ssc_rate > 0) {
uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
}
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
uniphier_ld20_dspll_init(SC_A2PLLCTRL);
return 0;
}

61
arch/arm/mach-uniphier/pll/pll-init-ld4.c → arch/arm/mach-uniphier/clk/pll-ld4.c
View File

@ -1,55 +1,17 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
static int dpll_init(unsigned int dram_freq)
{
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x000f0000;
switch (dram_freq) {
case 1333:
tmp |= 0x000d0000;
break;
case 1600:
tmp |= 0x000c0000;
break;
default:
pr_err("Unsupported frequency");
return -EINVAL;
}
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~SC_DPLLCTRL_SSC_RATE;
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
return 0;
}
#include "pll.h"
static void upll_init(void)
{
@ -183,22 +145,9 @@ static void vpll_init(void)
writel(tmp, SC_VPLL27BCTRL);
}
int uniphier_ld4_pll_init(const struct uniphier_board_data *bd)
void uniphier_ld4_pll_init(void)
{
int ret;
ret = dpll_init(bd->dram_freq);
if (ret)
return ret;
upll_init();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 10 usec in upll_init() and vpll_init()
* so 20 usec can be saved here.
*/
udelay(480);
return 0;
uniphier_ld4_dpll_ssc_en();
}

64
arch/arm/mach-uniphier/pll/pll-init-pro4.c → arch/arm/mach-uniphier/clk/pll-pro4.c
View File

@ -1,59 +1,17 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
#undef DPLL_SSC_RATE_1PER
static int dpll_init(unsigned int dram_freq)
{
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT ( DPLLCTRL.bit[29:20] )
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~(0x000f0000);
switch (dram_freq) {
case 1333:
tmp |= 0x000d0000;
break;
case 1600:
tmp |= 0x000c0000;
break;
default:
pr_err("Unsupported frequency");
return -EINVAL;
}
/*
* Set Moduration rate
* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
*/
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~0x00008000;
#else
tmp |= 0x00008000;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
return 0;
}
#include "pll.h"
static void vpll_init(void)
{
@ -145,20 +103,8 @@ static void vpll_init(void)
writel(tmp, SC_VPLL27BCTRL);
}
int uniphier_pro4_pll_init(const struct uniphier_board_data *bd)
void uniphier_pro4_pll_init(void)
{
int ret;
ret = dpll_init(bd->dram_freq);
if (ret)
return ret;
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 1 usec in vpll_init() so 1 usec can be saved here.
*/
udelay(499);
return 0;
uniphier_ld4_dpll_ssc_en();
}

14
arch/arm/mach-uniphier/clk/pll-sld3.c Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "pll.h"
void uniphier_sld3_pll_init(void)
{
uniphier_ld4_dpll_ssc_en();
}

21
arch/arm/mach-uniphier/clk/pll.h Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef MACH_PLL_H
#define MACH_PLL_H
#define UNIPHIER_PLL_FREQ_DEFAULT (0)
void uniphier_ld4_dpll_ssc_en(void);
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
unsigned int ssc_rate, unsigned int divn);
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
int uniphier_ld20_vpll27_init(unsigned long reg_base);
int uniphier_ld20_dspll_init(unsigned long reg_base);
#endif /* MACH_PLL_H */

78
arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
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@ -1,41 +1,55 @@
/*
* Copyright (C) 2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
#define PHY_SCL_DATA_0 0x00000104
#define PHY_SCL_DATA_1 0x00000108
#define PHY_SCL_LATENCY 0x0000010C
#define PHY_SCL_START 0x00000100
#define PHY_SCL_CONFIG_1 0x00000118
#define PHY_SCL_CONFIG_2 0x0000011C
#define PHY_PAD_CTRL 0x00000120
#define PHY_DLL_RECALIB 0x00000124
#define PHY_DLL_ADRCTRL 0x00000128
#define PHY_LANE_SEL 0x0000012C
#define PHY_DLL_TRIM_1 0x00000130
#define PHY_DLL_TRIM_2 0x00000134
#define PHY_DLL_TRIM_3 0x00000138
#define PHY_SCL_MAIN_CLK_DELTA 0x00000140
#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C
#define PHY_WRLVL_DYN_ODT 0x00000150
#define PHY_WRLVL_ON_OFF 0x00000154
#define PHY_UNQ_ANALOG_DLL_1 0x0000015C
#define PHY_DLL_INCR_TRIM_1 0x00000164
#define PHY_DLL_INCR_TRIM_3 0x00000168
#define PHY_SCL_CONFIG_3 0x0000016C
#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170
#define PHY_SCL_START_ADDR 0x00000188
#define PHY_DSCL_CNT 0x0000019C
#define PHY_DLL_TRIM_CLK 0x000001A4
#define PHY_DYNAMIC_BIT_LVL 0x000001AC
#define PHY_SCL_WINDOW_TRIM 0x000001B4
#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8
#define PHY_SCL_CONFIG_4 0x000001BC
#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0
#define PHY_VREF_TRAINING 0x000001C8
#define PHY_SCL_GATE_TIMING 0x000001E0
#define PHY_REG_SHIFT 2
#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT))
#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT))
#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT))
#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT))
#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT))
#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT))
#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT))
#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT))
#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT))
#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT))
#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
/* MASK */
#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F
#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F
#define MSK_OVERRIDE 0x00000080
#define PHY_BITLVL_DLY_WIDTH 6
#endif /* _DDRPHY_LD20_REGS_H */

433
arch/arm/mach-uniphier/dram/umc-ld20.c
View File

@ -1,7 +1,7 @@
/*
* Copyright (C) 2016 Socionext Inc.
*
* based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
* based on commit a3c28918e86ad57127cf07bf8b32950cab20c03c of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -18,6 +18,7 @@
#include "umc64-regs.h"
#define DRAM_CH_NR 3
#define CONFIG_DDR_FREQ 1866
enum dram_freq {
DRAM_FREQ_1866M,
@ -30,6 +31,268 @@ enum dram_size {
DRAM_SZ_NR,
};
enum dram_board { /* board type */
DRAM_BOARD_LD20_REF, /* LD20 reference */
DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
DRAM_BOARD_LD21_REF, /* LD21 reference */
DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
DRAM_BOARD_NR,
};
#define MSK_PHY_LANE_SEL 0x000000FF
#define MSK_BIT_SEL 0x00000F00
#define MSK_DLL_MAS_DLY 0xFF000000
#define MSK_MAS_DLY 0x7F000000
#define MSK_DLLS_TRIM_CLK 0x000000FF
#define PHY_DLL_MAS_DLY_WIDTH 8
#define PHY_SLV_DLY_WIDTH 6
static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
{
u32 value;
value = (readl(addr) & ~mask) | (data & mask);
writel(value, addr);
}
static u32 ddrphy_maskreadl(u32 mask, void *addr)
{
return readl(addr) & mask;
}
/* set phy_lane_sel.phy_lane_sel */
static void ddrphy_set_phy_lane_sel(int val, void __iomem *phy_base)
{
ddrphy_maskwritel(val, MSK_PHY_LANE_SEL, phy_base + PHY_LANE_SEL);
}
/* set phy_lane_sel.bit_sel */
static void ddrphy_set_bit_sel(int bit, void __iomem *phy_base)
{
ddrphy_maskwritel(bit << 8, MSK_BIT_SEL, phy_base + PHY_LANE_SEL);
}
/* Calculating step for PUB-byte */
static int ddrphy_hpstep(int delay, void __iomem *phy_base)
{
int mdl, freq;
freq = CONFIG_DDR_FREQ; /* FIXME */
mdl = ddrphy_maskreadl(MSK_DLL_MAS_DLY, phy_base + PHY_DLL_ADRCTRL) >> 24;
return DIV_ROUND_CLOSEST(freq * delay * mdl, 2 * 1000000);
}
static void ddrphy_set_dll_trim_clk(int delay_ckoffset, void __iomem *phy_base)
{
u8 ck_step; /* ckoffset_step for clock */
u32 ck_step_all;
/* CK-Offset */
if (delay_ckoffset >= 0) {
/* shift + direction */
ck_step = min(ddrphy_hpstep(delay_ckoffset, phy_base), 127);
ck_step_all = ((0x1<<(PHY_SLV_DLY_WIDTH + 1))|ck_step);
} else{
/* shift - direction */
ck_step = min(ddrphy_hpstep(-1*delay_ckoffset, phy_base), 127);
ck_step_all = ck_step;
}
ddrphy_set_phy_lane_sel(0, phy_base);
ddrphy_maskwritel(ck_step_all, MSK_DLLS_TRIM_CLK, phy_base + PHY_DLL_TRIM_CLK);
}
static void ddrphy_set_dll_recalib(int delay_qoffset, u32 recalib_cnt,
u8 disable_recalib, u8 ctr_start_val,
void __iomem *phy_base)
{
u8 dlls_trim_adrctrl_ma, incr_dly_adrctrl_ma; /* qoffset_step and flag for inc/dec */
u32 recalib_all; /* all fields of register dll_recalib */
/* Q-Offset */
if (delay_qoffset >= 0) {
dlls_trim_adrctrl_ma = min(ddrphy_hpstep(delay_qoffset, phy_base), 63);
incr_dly_adrctrl_ma = 0x1;
} else {
dlls_trim_adrctrl_ma = min(ddrphy_hpstep(-1*delay_qoffset, phy_base), 63);
incr_dly_adrctrl_ma = 0x0;
}
recalib_all = ((ctr_start_val & 0xf) << 28) |
(incr_dly_adrctrl_ma << 27) |
((disable_recalib & 0x1) << 26) |
((recalib_cnt & 0x3ffff) << 8) |
(dlls_trim_adrctrl_ma & 0x3f);
/* write value for all bits other than bit[7:6] */
ddrphy_maskwritel(recalib_all, ~0xc0, phy_base + PHY_DLL_RECALIB);
}
static void ddrphy_set_dll_adrctrl(int delay_qoffset, u8 override_adrctrl,
void __iomem *phy_base)
{
u8 dlls_trim_adrctrl, incr_dly_adrctrl; /* qoffset_step for clock */
u32 adrctrl_all;
if (delay_qoffset >= 0) {
dlls_trim_adrctrl = min(ddrphy_hpstep(delay_qoffset, phy_base), 63);
incr_dly_adrctrl = 0x1;
} else {
dlls_trim_adrctrl = min(ddrphy_hpstep(-delay_qoffset, phy_base), 63);
incr_dly_adrctrl = 0x0;
}
adrctrl_all = (incr_dly_adrctrl << 9) |
((override_adrctrl & 0x1) << 8) |
dlls_trim_adrctrl;
ddrphy_maskwritel(adrctrl_all, 0x33f, phy_base + PHY_DLL_ADRCTRL);
}
/* dio */
static int dio_adrctrl_0[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268-262, 268-263, 268-378}, /* LD20 reference */
{268-262, 268-263, 268-378}, /* LD20 TV */
{268-212, 268-268, 0}, /* LD21 reference */
{268-212, 268-268, 0}, /* LD21 TV */
};
static int dio_dlltrimclk_0[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268, 268, 268}, /* LD20 reference */
{268, 268, 268}, /* LD20 TV */
{268, 268+252, 0}, /* LD21 reference */
{268, 268+202, 0}, /* LD21 TV */
};
static int dio_dllrecalib_0[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268-378, 268-263, 268-378}, /* LD20 reference */
{268-378, 268-263, 268-378}, /* LD20 TV */
{268-212, 268-536, 0}, /* LD21 reference */
{268-212, 268-536, 0}, /* LD21 TV */
};
static u32 dio_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
{0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
{0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 reference */
{0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 TV */
};
static u32 dio_scl_gate_timing[DRAM_CH_NR] = {0x00000140, 0x00000180, 0x00000140};
static int dio_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
{ /* LD20 reference */
{
2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1,
1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1,
},
{
1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1,
},
{
2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1,
2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2,
},
},
{ /* LD20 TV */
{
2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1,
1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1,
},
{
1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1,
},
{
2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1,
2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2,
},
},
{ /* LD21 reference */
{
1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2,
1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1,
},
{ 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0,
1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0,
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
},
{ /* LD21 TV */
{
1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2,
1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1,
},
{ 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0,
1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0,
},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
},
};
static int dio_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
{ /* LD20 reference */
{
3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2,
2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2,
},
{
2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2,
2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
},
{
2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3,
2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1,
},
},
{ /* LD20 TV */
{
3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2,
2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2,
},
{
2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2,
2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
},
{
2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3,
2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1,
},
},
{ /* LD21 reference */
{
2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2,
2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2,
},
{
3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2,
1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1,
},
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
},
{ /* LD21 TV */
{
2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2,
2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2,
},
{
3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2,
1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1,
},
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
},
};
/* umc */
static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
@ -37,15 +300,24 @@ static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00000601, 0x00000801}, /* 1866 MHz */
};
static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00000120, 0x00000130}, /* 1866 MHz */
};
static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00033603, 0x00033803}, /* 1866 MHz */
};
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
{0x0049071D, 0x0078071D},
/* 256MB 512MB */
{0x0049071D, 0x0078071D}, /* 1866 MHz */
};
static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
@ -61,12 +333,22 @@ static u32 umc_directbusctrla[DRAM_CH_NR] = {
0x00000000, 0x00000001, 0x00000001
};
/* DDR PHY */
static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
/* polling function for PHY Init Complete */
static void ddrphy_init_complete(void __iomem *dc_base)
{
writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
/* Wait for PHY Init Complete */
while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
cpu_relax();
}
/* DDR PHY */
static void ddrphy_init(void __iomem *phy_base, void __iomem *dc_base,
enum dram_freq freq, enum dram_board board, int ch)
{
writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
cpu_relax();
writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
@ -84,14 +366,14 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
writel(dio_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
writel(0x00000070, phy_base + PHY_VREF_TRAINING);
writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
writel(dio_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
@ -99,30 +381,96 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
writel(0x00005076, phy_base + PHY_SCL_LATENCY);
ddrphy_init_complete(dc_base);
ddrphy_set_dll_adrctrl(dio_adrctrl_0[board][ch], 0, phy_base);
ddrphy_set_dll_trim_clk(dio_dlltrimclk_0[board][ch], phy_base);
ddrphy_set_dll_recalib(dio_dllrecalib_0[board][ch], 0x10, 0, 0xa,
phy_base);
}
static int ddrphy_training(void __iomem *phy_base)
static void ddrphy_shift_dq(u32 reg_mask, u32 reg_addr, int shift_val,
void __iomem *phy_base)
{
u32 reg_val;
int dq_val;
reg_val = ddrphy_maskreadl(reg_mask, phy_base + reg_addr) & 0x7f;
dq_val = reg_val & 0x3f;
if ((reg_val & 0x40) == 0x00)
dq_val = -1 * dq_val;
/* value shift*/
dq_val = dq_val + shift_val;
if (dq_val >= 0)
reg_val = 0x40 + (dq_val & 0x3f);
else
reg_val = ((-1 * dq_val) & 0x3f);
ddrphy_maskwritel(reg_val, reg_mask, phy_base + reg_addr);
}
static void ddrphy_shift(void __iomem *phy_base, enum dram_board board, int ch)
{
u32 dx, bit;
/* set override = 1 */
ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE,
phy_base + PHY_OP_DQ_DM_DQS_BITWISE_TRIM);
ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE,
phy_base + PHY_IP_DQ_DQS_BITWISE_TRIM);
for (dx = 0; dx < 4; dx++) {
/* set byte to PHY_LANE_SEL.phy_lane_sel= dx * (PHY_BITLVL_DLY_WIDTH+1) */
ddrphy_set_phy_lane_sel(dx * (PHY_BITLVL_DLY_WIDTH + 1),
phy_base);
for (bit = 0; bit < 8; bit++) {
ddrphy_set_bit_sel(bit, phy_base);
/* shift write reg value*/
ddrphy_shift_dq(MSK_OP_DQ_DM_DQS_BITWISE_TRIM,
PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
dio_op_dq_shift_val[board][ch][dx * 8 + bit],
phy_base);
/* shift read reg value */
ddrphy_shift_dq(MSK_IP_DQ_DQS_BITWISE_TRIM,
PHY_IP_DQ_DQS_BITWISE_TRIM,
dio_ip_dq_shift_val[board][ch][dx * 8 + bit],
phy_base);
}
}
ddrphy_set_phy_lane_sel(0, phy_base);
ddrphy_set_bit_sel(0, phy_base);
}
static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
int ch)
{
writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
writel(0x50000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
while (readl(phy_base + PHY_SCL_START) & BIT(28))
cpu_relax();
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x11000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
while (readl(phy_base + PHY_SCL_START) & BIT(28))
cpu_relax();
writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x30500000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
while (readl(phy_base + PHY_SCL_START) & BIT(28))
cpu_relax();
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
@ -131,16 +479,22 @@ static int ddrphy_training(void __iomem *phy_base)
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
writel(0x11000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
while (readl(phy_base + PHY_SCL_START) & BIT(28))
cpu_relax();
writel(0x34000000, phy_base + PHY_SCL_START);
while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
while (readl(phy_base + PHY_SCL_START) & BIT(28))
cpu_relax();
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL);
writel(0x011BD0C4, phy_base + PHY_DSCL_CNT);
/* shift ip_dq, op_dq trim */
ddrphy_shift(phy_base, board, ch);
return 0;
}
@ -164,10 +518,6 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
return -EINVAL;
}
/* Wait for PHY Init Complete */
while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
cpu_relax();
writel(0x00000001, dc_base + UMC_DFICSOVRRD);
writel(0x00000000, dc_base + UMC_DFITURNOFF);
@ -180,9 +530,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
writel(0x00000000, dc_base + UMC_DRMMR3);
writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
writel(umc_memconf0a[freq][size_e], dc_base + UMC_MEMCONF0A);
writel(umc_memconf0b[freq][size_e], dc_base + UMC_MEMCONF0B);
writel(umc_memconfch[freq][size_e], dc_base + UMC_MEMCONFCH);
writel(0x00000008, dc_base + UMC_MEMMAPSET);
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
@ -227,7 +577,8 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
}
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
enum dram_freq freq, unsigned long size, int ch)
enum dram_freq freq, enum dram_board board,
unsigned long size, int ch)
{
void __iomem *dc_base = umc_ch_base + 0x00011000;
void __iomem *phy_base = phy_ch_base;
@ -240,13 +591,13 @@ static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
dc_base + UMC_DIOCTLA);
ddrphy_init(phy_base, freq);
ddrphy_init(phy_base, dc_base, freq, board, ch);
ret = umc_dc_init(dc_base, freq, size, ch);
if (ret)
return ret;
ret = ddrphy_training(phy_base);
ret = ddrphy_training(phy_base, board, ch);
if (ret)
return ret;
@ -274,6 +625,7 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
enum dram_freq freq;
enum dram_board board;
int ch, ret;
switch (bd->dram_freq) {
@ -285,11 +637,30 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
return -EINVAL;
}
switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) {
case UNIPHIER_BD_BOARD_LD20_REF:
board = DRAM_BOARD_LD20_REF;
break;
case UNIPHIER_BD_BOARD_LD20_GLOBAL:
board = DRAM_BOARD_LD20_GLOBAL;
break;
case UNIPHIER_BD_BOARD_LD21_REF:
board = DRAM_BOARD_LD21_REF;
break;
case UNIPHIER_BD_BOARD_LD21_GLOBAL:
board = DRAM_BOARD_LD21_GLOBAL;
break;
default:
pr_err("unsupported board type %d\n",
UNIPHIER_BD_BOARD_GET_TYPE(bd->flags));
return -EINVAL;
}
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, board,
size / (width / 16), ch);
if (ret) {
pr_err("failed to initialize UMC ch%d\n", ch);

13
arch/arm/mach-uniphier/early-clk/Makefile
View File

@ -1,13 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o

7
arch/arm/mach-uniphier/early-pinctrl/Makefile
View File

@ -1,7 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-pinctrl-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o

32
arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sg-regs.h"
int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd)
{
/* Comment format: PAD Name -> Function Name */
sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */
sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */
sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */
sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */
sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */
sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */
sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */
sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */
sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */
sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */
sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */
sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */
sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */
sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */
sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */
sg_set_iectrl_range(0, 2);
sg_set_iectrl_range(6, 17);
return 0;
}

28
arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c
View File

@ -1,28 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sg-regs.h"
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
#endif
sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
return 0;
}

43
arch/arm/mach-uniphier/init.h
View File

@ -23,9 +23,17 @@ struct uniphier_board_data {
unsigned int dram_nr_ch;
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
#define UNIPHIER_BD_DDR3PLUS BIT(2)
#define UNIPHIER_BD_PACKAGE_LD21 1
#define UNIPHIER_BD_PACKAGE_TYPE(f) ((f) & 0x3)
#define UNIPHIER_BD_DPLL_SSC_GET_RATE(f) (((f) >> 8) & 0x3)
#define UNIPHIER_BD_DPLL_SSC_RATE(r) (((r) & 0x3) << 8)
#define UNIPHIER_BD_DDR3PLUS BIT(2)
#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x3)
#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */
#define UNIPHIER_BD_BOARD_LD21_REF 2 /* LD21 reference */
#define UNIPHIER_BD_BOARD_LD21_GLOBAL 3 /* LD21 TV Set */
};
const struct uniphier_board_data *uniphier_get_board_param(void);
@ -75,13 +83,11 @@ int memconf_init(const struct uniphier_board_data *bd);
int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
int uniphier_sld3_pll_init(const struct uniphier_board_data *bd);
int uniphier_ld4_pll_init(const struct uniphier_board_data *bd);
int uniphier_pro4_pll_init(const struct uniphier_board_data *bd);
int uniphier_sld8_pll_init(const struct uniphier_board_data *bd);
int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
@ -89,9 +95,6 @@ int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
@ -99,14 +102,10 @@ int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pin_init(void);
void uniphier_ld4_pin_init(void);
void uniphier_pro4_pin_init(void);
void uniphier_sld8_pin_init(void);
void uniphier_pro5_pin_init(void);
void uniphier_pxs2_pin_init(void);
void uniphier_ld6b_pin_init(void);
void uniphier_ld20_pin_init(void);
void uniphier_sld3_pll_init(void);
void uniphier_ld4_pll_init(void);
void uniphier_pro4_pll_init(void);
int uniphier_ld20_pll_init(const struct uniphier_board_data *bd);
void uniphier_ld4_clk_init(void);
void uniphier_pro4_clk_init(void);
@ -115,6 +114,8 @@ void uniphier_pxs2_clk_init(void);
void uniphier_ld11_clk_init(void);
void uniphier_ld20_clk_init(void);
int uniphier_pin_init(const char *pinconfig_name);
void uniphier_smp_kick_all_cpus(void);
void cci500_init(int nr_slaves);
#define pr_err(fmt, args...) printf(fmt, ##args)

2
arch/arm/mach-uniphier/init/init-ld11.c
View File

@ -15,7 +15,7 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
uniphier_ld20_early_pin_init(bd);
uniphier_pin_init("system_bus_grp");
support_card_reset();

11
arch/arm/mach-uniphier/init/init-ld20.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -14,7 +15,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
{
uniphier_sbc_init_savepin(bd);
uniphier_pxs2_sbc_init(bd);
uniphier_ld20_early_pin_init(bd);
uniphier_pin_init("system_bus_grp");
support_card_reset();
@ -31,12 +32,14 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
led_puts("L2");
led_puts("L3");
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_puts("L3");
uniphier_ld20_dpll_init(bd);
led_puts("L4");
{

10
arch/arm/mach-uniphier/init/init-ld4.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2013-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -19,7 +21,7 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
support_card_reset();
uniphier_ld4_pll_init(bd);
uniphier_ld4_dpll_init(bd);
support_card_init();
@ -53,9 +55,5 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
led_puts("L5");
uniphier_ld4_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

10
arch/arm/mach-uniphier/init/init-pro4.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2013-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -16,7 +18,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd)
support_card_reset();
uniphier_pro4_pll_init(bd);
uniphier_pro4_dpll_init(bd);
support_card_init();
@ -50,9 +52,5 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd)
led_puts("L5");
uniphier_ld4_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

12
arch/arm/mach-uniphier/init/init-sld3.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2013-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -16,11 +18,9 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
uniphier_sbc_init_admulti(bd);
uniphier_sld3_early_pin_init(bd);
support_card_reset();
uniphier_sld3_pll_init(bd);
uniphier_sld3_dpll_init(bd);
support_card_init();
@ -45,9 +45,5 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
led_puts("L5");
uniphier_sld3_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

10
arch/arm/mach-uniphier/init/init-sld8.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2013-2015 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -19,7 +21,7 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
support_card_reset();
uniphier_sld8_pll_init(bd);
uniphier_sld8_dpll_init(bd);
support_card_init();
@ -53,9 +55,5 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
led_puts("L5");
uniphier_ld4_enable_dpll_ssc(bd);
led_puts("L6");
return 0;
}

2
arch/arm/mach-uniphier/micro-support-card.c
View File

@ -49,7 +49,7 @@ static int support_card_show_revision(void)
return 0;
}
int check_support_card(void)
int checkboard(void)
{
printf("SC: Micro Support Card ");
return support_card_show_revision();

16
arch/arm/mach-uniphier/micro-support-card.h
View File

@ -1,17 +1,18 @@
/*
* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2012-2014 Panasonic Corporation
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BOARD_H
#define ARCH_BOARD_H
#ifndef MICRO_SUPPORT_CARD_H
#define MICRO_SUPPORT_CARD_H
#if defined(CONFIG_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
void support_card_late_init(void);
int check_support_card(void);
void led_puts(const char *s);
#else
static inline void support_card_reset(void)
@ -26,14 +27,9 @@ static inline void support_card_late_init(void)
{
}
static inline int check_support_card(void)
{
return 0;
}
static inline void led_puts(const char *s)
{
}
#endif
#endif /* ARCH_BOARD_H */
#endif /* MICRO_SUPPORT_CARD_H */

32
arch/arm/mach-uniphier/pinctrl-glue.c Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/err.h>
#include <dm/device.h>
#include <dm/pinctrl.h>
#include <dm/uclass.h>
#include "init.h"
int uniphier_pin_init(const char *pinconfig_name)
{
struct udevice *pctldev, *config, *next;
int ret;
ret = uclass_first_device(UCLASS_PINCTRL, &pctldev);
if (ret)
return ret;
device_foreach_child_safe(config, next, pctldev) {
if (strcmp(config->name, pinconfig_name))
continue;
return pinctrl_generic_set_state(pctldev, config);
}
return -ENODEV;
}

13
arch/arm/mach-uniphier/pinctrl/Makefile
View File

@ -1,13 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pinctrl-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pinctrl-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pinctrl-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o
obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o
obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o

51
arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c
View File

@ -1,51 +0,0 @@
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_ld20_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */
sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */
sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */
sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */
sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */
sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */
sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */
sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */
sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */
sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */
sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */
sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */
sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */
sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */
sg_set_iectrl_range(3, 17);
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */
sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */
sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */
sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */
sg_set_iectrl_range(46, 53);
#endif
sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
sg_set_iectrl(149);
sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
sg_set_iectrl(153);
}

41
arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c
View File

@ -1,41 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_ld4_pin_init(void)
{
u32 tmp;
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
#endif
tmp = readl(SG_IECTRL);
tmp |= 0x41;
writel(tmp, SG_IECTRL);
}

46
arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c
View File

@ -1,46 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_ld6b_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */
sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */
sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */
sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */
sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */
sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */
sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */
sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */
sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */
sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */
sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */
sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */
sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */
sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */
sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */
sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */
sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */
sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */
sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */
#endif
}

44
arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c
View File

@ -1,44 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_pro4_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */
sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */
sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */
sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */
sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */
sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */
sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */
sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */
sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */
sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */
sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */
sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */
sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */
sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
/* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */
/* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */
sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
#endif
writel(1, SG_LOADPINCTRL);
}

44
arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c
View File

@ -1,44 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_pro5_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */
sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */
sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */
sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */
sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */
sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */
sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */
sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */
sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */
sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */
sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */
sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */
sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */
sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */
sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */
sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */
#endif
writel(1, SG_LOADPINCTRL);
}

46
arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c
View File

@ -1,46 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_pxs2_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */
sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */
sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */
sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */
sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */
sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */
sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */
sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */
sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */
sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */
sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */
sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */
sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */
sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */
sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */
sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */
sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */
sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */
sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */
#endif
}

48
arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c
View File

@ -1,48 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sg-regs.h"
void uniphier_sld3_pin_init(void)
{
#ifdef CONFIG_USB_EHCI
sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */
sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */
sg_set_pinsel(40, 1, 4, 4); /* XNFCE0_GB, XNFRE_GB, XNFWE_GB, XNFWP_GB */
sg_set_pinsel(41, 1, 4, 4); /* XNFRYBY1_GB, XNFCE1_GB */
sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */
sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */
#endif
#ifdef CONFIG_MMC_UNIPHIER
/* eMMC */
sg_set_pinsel(55, 1, 4, 4); /* XERST */
sg_set_pinsel(56, 1, 4, 4); /* MMCDAT[0-3] */
sg_set_pinsel(57, 1, 4, 4); /* MMCDAT[4-7] */
sg_set_pinsel(60, 1, 4, 4); /* MMCCLK, MMCCMD */
/* SD card */
sg_set_pinsel(42, 1, 4, 4); /* SD1CLK, SD1CMD, SD1DAT[0-3] */
sg_set_pinsel(43, 1, 4, 4); /* SD1CD */
sg_set_pinsel(44, 1, 4, 4); /* SD1WP */
sg_set_pinsel(45, 1, 4, 4); /* SDVTCG */
#endif
}

35
arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c
View File

@ -1,35 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sg-regs.h"
void uniphier_sld8_pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
#endif
}

8
arch/arm/mach-uniphier/pll/Makefile
View File

@ -1,8 +0,0 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o pll-spectrum-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o pll-spectrum-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o pll-spectrum-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o pll-spectrum-ld4.o

205
arch/arm/mach-uniphier/pll/pll-init-sld8.c
View File

@ -1,205 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
#include "../sg-regs.h"
static void dpll_init(void)
{
u32 tmp;
/*
* Set DPLL SSC parameters for DPLLCTRL3
* [23] DIVN_TEST 0x1
* [22:16] DIVN 0x50
* [10] FREFSEL_TEST 0x1
* [9:8] FREFSEL 0x2
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
tmp = readl(SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
writel(tmp, SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
* <-1%> <-2%>
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef CONFIG_DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
writel(tmp, SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
* [31:29] SSC_STEP 0
* [27] SSC_REG_REF 1
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
tmp = readl(SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
writel(tmp, SC_DPLLCTRL2);
}
static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
tmp = readl(SC_UPLLCTRL);
tmp &= ~0x18000000;
writel(tmp, SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp &= ~0x07ffffff;
tmp |= 0x0228f5c0;
} else {
/* AXO: default 24.576MHz */
tmp &= ~0x07ffffff;
tmp |= 0x02328000;
}
}
writel(tmp, SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
writel(tmp, SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
writel(tmp, SC_UPLLCTRL);
}
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
int uniphier_sld8_pll_init(const struct uniphier_board_data *bd)
{
dpll_init();
upll_init();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 10 usec in upll_init() and vpll_init()
* so 20 usec can be saved here.
*/
udelay(480);
return 0;
}

21
arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
View File

@ -1,21 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
return 0;
}

22
arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c
View File

@ -1,22 +0,0 @@
/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc-regs.h"
int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
return 0;
}

12
arch/arm/mach-uniphier/print_misc_info.c
View File

@ -1,12 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "micro-support-card.h"
int misc_init_f(void)
{
return check_support_card();
}

22
arch/arm/mach-uniphier/sc64-regs.h
View File

@ -1,7 +1,8 @@
/*
* UniPhier SC (System Control) block registers for ARMv8 SoCs
*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -11,6 +12,25 @@
#define SC_BASE_ADDR 0x61840000
/* PLL type: SSC */
#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD20: CPU/ARM */
#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD20: misc */
#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD20: Video codec */
#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
/* PLL type: VPLL27 */
#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
/* PLL type: DSPLL */
#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)

2
configs/uniphier_ld11_defconfig
View File

@ -24,8 +24,6 @@ CONFIG_SPL_OF_TRANSLATE=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y

2
configs/uniphier_ld20_defconfig
View File

@ -25,8 +25,6 @@ CONFIG_GPIO_UNIPHIER=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y

3
configs/uniphier_ld4_sld8_defconfig
View File

@ -30,10 +30,7 @@ CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

4
configs/uniphier_pro4_defconfig
View File

@ -29,8 +29,8 @@ CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

2
configs/uniphier_pxs2_ld6b_defconfig
View File

@ -30,8 +30,6 @@ CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=y

1
configs/uniphier_sld3_defconfig
View File

@ -31,7 +31,6 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y

1
drivers/mmc/Kconfig
View File

@ -80,6 +80,7 @@ config ROCKCHIP_SDHCI
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
depends on BLK
select DM_MMC_OPS
help
This selects support for the SD/MMC Host Controller on UniPhier SoCs.

50
drivers/mmc/uniphier-sd.c
View File

@ -119,9 +119,12 @@ DECLARE_GLOBAL_DATA_PTR;
/* alignment required by the DMA engine of this controller */
#define UNIPHIER_SD_DMA_MINALIGN 0x10
struct uniphier_sd_priv {
struct uniphier_sd_plat {
struct mmc_config cfg;
struct mmc *mmc;
struct mmc mmc;
};
struct uniphier_sd_priv {
void __iomem *regbase;
unsigned long mclk;
unsigned int version;
@ -654,8 +657,16 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
}
}
static int uniphier_sd_bind(struct udevice *dev)
{
struct uniphier_sd_plat *plat = dev_get_platdata(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
static int uniphier_sd_probe(struct udevice *dev)
{
struct uniphier_sd_plat *plat = dev_get_platdata(dev);
struct uniphier_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
@ -691,15 +702,15 @@ static int uniphier_sd_probe(struct udevice *dev)
return ret;
}
priv->cfg.name = dev->name;
priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
plat->cfg.name = dev->name;
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
case 8:
priv->cfg.host_caps |= MMC_MODE_8BIT;
plat->cfg.host_caps |= MMC_MODE_8BIT;
break;
case 4:
priv->cfg.host_caps |= MMC_MODE_4BIT;
plat->cfg.host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
@ -722,27 +733,13 @@ static int uniphier_sd_probe(struct udevice *dev)
uniphier_sd_host_init(priv);
priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
priv->cfg.f_min = priv->mclk /
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
plat->cfg.f_min = priv->mclk /
(priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
priv->cfg.f_max = priv->mclk;
priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
plat->cfg.f_max = priv->mclk;
plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
priv->mmc = mmc_create(&priv->cfg, priv);
if (!priv->mmc)
return -EIO;
upriv->mmc = priv->mmc;
priv->mmc->dev = dev;
return 0;
}
static int uniphier_sd_remove(struct udevice *dev)
{
struct uniphier_sd_priv *priv = dev_get_priv(dev);
mmc_destroy(priv->mmc);
upriv->mmc = &plat->mmc;
return 0;
}
@ -756,8 +753,9 @@ U_BOOT_DRIVER(uniphier_mmc) = {
.name = "uniphier-mmc",
.id = UCLASS_MMC,
.of_match = uniphier_sd_match,
.bind = uniphier_sd_bind,
.probe = uniphier_sd_probe,
.remove = uniphier_sd_remove,
.priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
.platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
.ops = &uniphier_sd_ops,
};

6
drivers/pinctrl/uniphier/Kconfig
View File

@ -3,6 +3,12 @@ if ARCH_UNIPHIER
config PINCTRL_UNIPHIER
bool
config PINCTRL_UNIPHIER_SLD3
bool "UniPhier PH1-sLD3 SoC pinctrl driver"
depends on ARCH_UNIPHIER_SLD3
default y
select PINCTRL_UNIPHIER
config PINCTRL_UNIPHIER_LD4
bool "UniPhier PH1-LD4 SoC pinctrl driver"
depends on ARCH_UNIPHIER_LD4

1
drivers/pinctrl/uniphier/Makefile
View File

@ -4,6 +4,7 @@
obj-y += pinctrl-uniphier-core.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o

24
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
View File

@ -13,6 +13,10 @@
#include "pinctrl-uniphier.h"
#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
#define UNIPHIER_PINCTRL_IECTRL 0x1d00
static const char *uniphier_pinctrl_dummy_name = "_dummy";
static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
@ -101,8 +105,10 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
int muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
bool load_pinctrl;
unsigned reg, reg_end, shift, mask;
unsigned mux_bits = 8;
unsigned reg_stride = 4;
bool load_pinctrl = false;
u32 tmp;
/* some pins need input-enabling */
@ -111,24 +117,18 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
if (muxval < 0)
return; /* dedicated pin; nothing to do for pin-mux */
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
mux_bits = 4;
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
/*
* Mode offset bit
* Normal 4 * n shift+3:shift
* Debug 4 * n shift+7:shift+4
*/
mux_bits = 4;
mux_bits /= 2;
reg_stride = 8;
load_pinctrl = true;
} else {
/*
* Mode offset bit
* Normal 8 * n shift+3:shift
* Debug 8 * n + 4 shift+3:shift
*/
mux_bits = 8;
reg_stride = 4;
load_pinctrl = false;
}
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;

9
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
View File

@ -28,6 +28,12 @@ static const int i2c4_muxvals[] = {1, 1};
static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17};
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17};
static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2};
static const unsigned system_bus_cs1_pins[] = {0};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned uart0_pins[] = {54, 55};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {58, 59};
@ -52,6 +58,8 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@ -69,6 +77,7 @@ static const char * const uniphier_ld11_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

9
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
View File

@ -34,6 +34,12 @@ static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */
static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17};
static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2};
static const unsigned system_bus_cs1_pins[] = {0};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned uart0_pins[] = {54, 55};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {58, 59};
@ -62,6 +68,8 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP_SPL(system_bus),
UNIPHIER_PINCTRL_GROUP_SPL(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@ -82,6 +90,7 @@ static const char * const uniphier_ld20_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION_SPL(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

18
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View File

@ -51,6 +51,18 @@ static const unsigned nand_cs1_pins[] = {22, 23};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned system_bus_pins[] = {16, 17, 18, 19, 20, 165, 166, 167,
168, 169, 170, 171, 172, 173};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1,
-1, -1, -1};
static const unsigned system_bus_cs0_pins[] = {155};
static const int system_bus_cs0_muxvals[] = {1};
static const unsigned system_bus_cs1_pins[] = {174};
static const int system_bus_cs1_muxvals[] = {-1};
static const unsigned system_bus_cs2_pins[] = {64};
static const int system_bus_cs2_muxvals[] = {1};
static const unsigned system_bus_cs3_pins[] = {156};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned uart0_pins[] = {85, 88};
static const int uart0_muxvals[] = {1, 1};
static const unsigned uart1_pins[] = {155, 156};
@ -82,6 +94,11 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart1b),
@ -103,6 +120,7 @@ static const char * const uniphier_ld4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

21
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View File

@ -48,6 +48,20 @@ static const unsigned nand_cs1_pins[] = {37, 38};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0};
static const unsigned system_bus_cs1_pins[] = {14};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned system_bus_cs2_pins[] = {37};
static const int system_bus_cs2_muxvals[] = {6};
static const unsigned system_bus_cs3_pins[] = {38};
static const int system_bus_cs3_muxvals[] = {6};
static const unsigned system_bus_cs4_pins[] = {115};
static const int system_bus_cs4_muxvals[] = {6};
static const unsigned system_bus_cs5_pins[] = {55};
static const int system_bus_cs5_muxvals[] = {6};
static const unsigned uart0_pins[] = {135, 136};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0b_pins[] = {11, 12};
@ -81,6 +95,12 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
@ -103,6 +123,7 @@ static const char * const uniphier_ld6b_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

30
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View File

@ -53,6 +53,26 @@ static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
327};
static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned system_bus_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0};
static const unsigned system_bus_cs0_pins[] = {318};
static const int system_bus_cs0_muxvals[] = {5};
static const unsigned system_bus_cs1_pins[] = {24};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned system_bus_cs2_pins[] = {315};
static const int system_bus_cs2_muxvals[] = {5};
static const unsigned system_bus_cs3_pins[] = {313};
static const int system_bus_cs3_muxvals[] = {5};
static const unsigned system_bus_cs4_pins[] = {305};
static const int system_bus_cs4_muxvals[] = {5};
static const unsigned system_bus_cs5_pins[] = {303};
static const int system_bus_cs5_muxvals[] = {6};
static const unsigned system_bus_cs6_pins[] = {307};
static const int system_bus_cs6_muxvals[] = {6};
static const unsigned system_bus_cs7_pins[] = {312};
static const int system_bus_cs7_muxvals[] = {6};
static const unsigned uart0_pins[] = {127, 128};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {129, 130};
@ -86,6 +106,15 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(sd1),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@ -109,6 +138,7 @@ static const char * const uniphier_pro4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(sd1),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

30
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View File

@ -50,6 +50,26 @@ static const unsigned nand_cs1_pins[] = {26, 27};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned system_bus_pins[] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0};
static const unsigned system_bus_cs0_pins[] = {105};
static const int system_bus_cs0_muxvals[] = {1};
static const unsigned system_bus_cs1_pins[] = {18};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned system_bus_cs2_pins[] = {106};
static const int system_bus_cs2_muxvals[] = {1};
static const unsigned system_bus_cs3_pins[] = {100};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned system_bus_cs4_pins[] = {101};
static const int system_bus_cs4_muxvals[] = {1};
static const unsigned system_bus_cs5_pins[] = {102};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned system_bus_cs6_pins[] = {69};
static const int system_bus_cs6_muxvals[] = {5};
static const unsigned system_bus_cs7_pins[] = {70};
static const int system_bus_cs7_muxvals[] = {5};
static const unsigned uart0_pins[] = {47, 48};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart0b_pins[] = {227, 228};
@ -81,6 +101,15 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
@ -101,6 +130,7 @@ static const char * const uniphier_pro5_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

9
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View File

@ -53,6 +53,12 @@ static const unsigned nand_cs1_pins[] = {37, 38};
static const int nand_cs1_muxvals[] = {8, 8};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13};
static const int system_bus_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
8};
static const unsigned system_bus_cs1_pins[] = {14};
static const int system_bus_cs1_muxvals[] = {8};
static const unsigned uart0_pins[] = {217, 218};
static const int uart0_muxvals[] = {8, 8};
static const unsigned uart0b_pins[] = {179, 180};
@ -89,6 +95,8 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
@ -114,6 +122,7 @@ static const char * const uniphier_pxs2_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

128
drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c Normal file
View File

@ -0,0 +1,128 @@
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dm/device.h>
#include <dm/pinctrl.h>
#include "pinctrl-uniphier.h"
static const unsigned emmc_pins[] = {55, 56, 60};
static const int emmc_muxvals[] = {1, 1, 1};
static const unsigned emmc_dat8_pins[] = {57};
static const int emmc_dat8_muxvals[] = {1};
static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
113};
static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
static const unsigned ether_rmii_pins[] = {35};
static const int ether_rmii_muxvals[] = {1};
static const unsigned i2c0_pins[] = {36};
static const int i2c0_muxvals[] = {0};
static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
static const int nand_muxvals[] = {1, 1, 1, 1, 1};
static const unsigned nand_cs1_pins[] = {41};
static const int nand_cs1_muxvals[] = {1};
static const unsigned sd_pins[] = {42, 43, 44, 45};
static const int sd_muxvals[] = {1, 1, 1, 1};
static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
77, 78, 79, 80, 88, 89, 91, 92, 99};
static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1};
static const unsigned system_bus_cs0_pins[] = {93};
static const int system_bus_cs0_muxvals[] = {1};
static const unsigned system_bus_cs1_pins[] = {94};
static const int system_bus_cs1_muxvals[] = {1};
static const unsigned system_bus_cs2_pins[] = {95};
static const int system_bus_cs2_muxvals[] = {1};
static const unsigned system_bus_cs3_pins[] = {96};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned system_bus_cs4_pins[] = {81};
static const int system_bus_cs4_muxvals[] = {1};
static const unsigned system_bus_cs5_pins[] = {82};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {63, 64};
static const int uart0_muxvals[] = {0, 1};
static const unsigned uart1_pins[] = {65, 66};
static const int uart1_muxvals[] = {0, 1};
static const unsigned uart2_pins[] = {96, 102};
static const int uart2_muxvals[] = {2, 2};
static const unsigned usb0_pins[] = {13, 14};
static const int usb0_muxvals[] = {0, 1};
static const unsigned usb1_pins[] = {15, 16};
static const int usb1_muxvals[] = {0, 1};
static const unsigned usb2_pins[] = {17, 18};
static const int usb2_muxvals[] = {0, 1};
static const unsigned usb3_pins[] = {19, 20};
static const int usb3_muxvals[] = {0, 1};
static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
UNIPHIER_PINCTRL_GROUP_SPL(emmc),
UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_mii),
UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
UNIPHIER_PINCTRL_GROUP(usb3)
};
static const char * const uniphier_sld3_functions[] = {
UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_mii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
UNIPHIER_PINMUX_FUNCTION(usb0),
UNIPHIER_PINMUX_FUNCTION(usb1),
UNIPHIER_PINMUX_FUNCTION(usb2),
UNIPHIER_PINMUX_FUNCTION(usb3),
};
static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
.groups = uniphier_sld3_groups,
.groups_count = ARRAY_SIZE(uniphier_sld3_groups),
.functions = uniphier_sld3_functions,
.functions_count = ARRAY_SIZE(uniphier_sld3_functions),
.caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
};
static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
{
return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
}
static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
{ .compatible = "socionext,uniphier-sld3-pinctrl" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
.name = "uniphier-sld3-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
.probe = uniphier_sld3_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
.ops = &uniphier_pinctrl_ops,
};

21
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View File

@ -65,6 +65,20 @@ static const unsigned nand_cs1_pins[] = {22, 23};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned system_bus_pins[] = {136, 137, 138, 139, 140, 141, 142,
143, 144, 145, 146, 147, 148, 149};
static const int system_bus_muxvals[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1};
static const unsigned system_bus_cs1_pins[] = {150};
static const int system_bus_cs1_muxvals[] = {-1};
static const unsigned system_bus_cs2_pins[] = {10};
static const int system_bus_cs2_muxvals[] = {1};
static const unsigned system_bus_cs3_pins[] = {11};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned system_bus_cs4_pins[] = {12};
static const int system_bus_cs4_muxvals[] = {1};
static const unsigned system_bus_cs5_pins[] = {13};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {70, 71};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart1_pins[] = {114, 115};
@ -92,6 +106,12 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP_SPL(uart0),
UNIPHIER_PINCTRL_GROUP_SPL(uart1),
UNIPHIER_PINCTRL_GROUP_SPL(uart2),
@ -111,6 +131,7 @@ static const char * const uniphier_sld8_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
UNIPHIER_PINMUX_FUNCTION_SPL(uart2),

9
drivers/pinctrl/uniphier/pinctrl-uniphier.h
View File

@ -13,10 +13,6 @@
#include <linux/kernel.h>
#include <linux/types.h>
#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
#define UNIPHIER_PINCTRL_IECTRL 0x1d00
#define UNIPHIER_PIN_ATTR_PACKED(iectrl) (iectrl)
static inline unsigned int uniphier_pin_get_iectrl(unsigned long data)
@ -71,8 +67,9 @@ struct uniphier_pinctrl_socdata {
const char * const *functions;
int functions_count;
unsigned caps;
#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \

7
drivers/usb/host/Kconfig
View File

@ -15,13 +15,6 @@ config USB_XHCI_HCD
if USB_XHCI_HCD
config USB_XHCI_UNIPHIER
bool "Support for UniPhier on-chip xHCI USB controller"
depends on ARCH_UNIPHIER
default y
---help---
Enables support for the on-chip xHCI controller on UniPhier SoCs.
config USB_XHCI_DWC3
bool "DesignWare USB3 DRD Core Support"
help

1
drivers/usb/host/Makefile
View File

@ -62,7 +62,6 @@ obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
# designware
obj-$(CONFIG_USB_DWC2) += dwc2.o

85
drivers/usb/host/xhci-uniphier.c
View File

@ -1,85 +0,0 @@
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <usb.h>
#include <fdtdec.h>
#include "xhci.h"
static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
{
DECLARE_GLOBAL_DATA_PTR;
int node_list[2];
fdt_addr_t addr;
int count;
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
COMPAT_SOCIONEXT_XHCI, node_list,
ARRAY_SIZE(node_list));
if (index >= count)
return -ENODEV;
addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
if (addr == FDT_ADDR_T_NONE)
return -ENODEV;
*base = (struct xhci_hccr *)addr;
return 0;
}
#define USB3_RST_CTRL 0x00100040
#define IOMMU_RST_N (1 << 5)
#define LINK_RST_N (1 << 4)
static void uniphier_xhci_reset(void __iomem *base, int on)
{
u32 tmp;
tmp = readl(base + USB3_RST_CTRL);
if (on)
tmp &= ~(IOMMU_RST_N | LINK_RST_N);
else
tmp |= IOMMU_RST_N | LINK_RST_N;
writel(tmp, base + USB3_RST_CTRL);
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
{
int ret;
struct xhci_hccr *cr;
struct xhci_hcor *or;
ret = get_uniphier_xhci_base(index, &cr);
if (ret < 0)
return ret;
uniphier_xhci_reset(cr, 0);
or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
*hccr = cr;
*hcor = or;
return 0;
}
void xhci_hcd_stop(int index)
{
int ret;
struct xhci_hccr *cr;
ret = get_uniphier_xhci_base(index, &cr);
if (ret < 0)
return;
uniphier_xhci_reset(cr, 1);
}

3
include/configs/uniphier.h
View File

@ -31,9 +31,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

1
include/fdtdec.h
View File

@ -148,7 +148,6 @@ enum fdt_compat_id {
COMPAT_INTEL_MICROCODE, /* Intel microcode update */
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */

1
lib/fdtdec.c
View File

@ -59,7 +59,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_MICROCODE, "intel,microcode"),
COMPAT(AMS_AS3722, "ams,as3722"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),