Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
The current way memsize.c is built just made a symlink into the directory
with SPL and then compiled it like any other file there. This was bad as that
broke the out-of-tree build.
The new way introduced in this patch uses the standard spl/Makefile methods
(CONFIG_SPL_LIBCOMMON_SUPPORT / CONFIG_SPL_LIBGENERIC_SUPPORT) to let files in
common/ be built. Because common/Makefile says memsize.c is always built (SPL
and non-SPL build), this fixes our issue with memsize.c out-of-tree build.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This moves SPL to common location so it can be reused by multiple boards. Also,
this commit adjusts M28 SoM to avoid breakage due to the move.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.
This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
added but just fix the checkpatch errors in the old file and remove
the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In board_init_f() the gd->bd pointer is not valid when dram_init() is called.
This only avoids dying because DRAM is at zero on Tegra2. The common ARM
routine sets up the banks in the same way anyway, so we can just remove this
code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This message is not required, since it is followed by an 'official' U-Boot
message.
U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23)
TEGRA2
Board: NVIDIA Seaboard
dynamic ram_size = 1073741824
DRAM: 1 GiB
becomes:
TEGRA2
Board: NVIDIA Seaboard
DRAM: 1 GiB
This is a separate commit since it changes behavior.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Since we have cache support built in we can remove Tegra's existing cache
initialization code amd other related dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some SOCs have do not start up with their 'main' CPU. The first U-Boot
code may then be executed with a CPU which does not have a CP15, or not a
useful one.
Here we split the initialization of CP15 into a separate call, which can
be performed later if required.
Once the main CPU is running, you should call cpu_init_cp15() to perform
this init as early as possible.
Existing ARMv7 boards which define CONFIG_SKIP_LOWLEVEL_INIT should not
need to change, this CP15 init is still skipped in that case. The only
impact for these boards is that the cpu_init_cp15() will be available
even if it is never used on these boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra2 boot path is more complicated than it needs to be. Since we want
to move to building most of U-Boot with ARMv7 and only a small part with
ARMv4T (for AVP) it should be as simple as possible.
This makes tegra2_start() into a simple function which either does AVP
init or A9 init depending on which core is running it. Both cores now
following the same init path, beginning at _start, and the special Tegra2
boot path code is no longer required.
Only two files need to be built for ARMv4T, and this is handled in the
Tegra2 CPU Makefile.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We want to move away from a special Tegra2 start-up, and just use
arch_cpu_init() instead. However, if we run board_init_f() from boot
we need to build it for ARMv4T, since the Tegra's AVP start-up CPU
does not support ARMv7.
The effect of this is to do the AVP init earlier, and in
arch_cpu_init(), rather that board_early_init_f().
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Sorry if this is already fixed somewhere - I could not find it.
This fixes these warnings:
usb_ohci.c: In function 'submit_control_msg':
usb_ohci.c:1081: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1081: note: initialized from here
usb_ohci.c:1084: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1084: note: initialized from here
usb_ohci.c:1087: warning: dereferencing pointer 'data_buf.76' does break strict-aliasing rules
usb_ohci.c:1087: note: initialized from here
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Fix:
clocks.c: In function 'setup_post_dividers':
clocks.c:175: warning: comparison is always true due to limited range of
data type
clocks.c:177: warning: comparison is always true due to limited range of
data type
clocks.c:179: warning: comparison is always true due to limited range of
data type
clocks.c:181: warning: comparison is always true due to limited range of
data type
clocks.c:183: warning: comparison is always true due to limited range of
data type
clocks.c:185: warning: comparison is always true due to limited range of
data type
clocks.c:187: warning: comparison is always true due to limited range of
data type
clocks.c:189: warning: comparison is always true due to limited range of
data type
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Fix:
clocks-common.c: In function 'setup_dplls':
clocks-common.c:256:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:292:6: warning: variable 'sysclk_ind' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
Fix:
spl.c: In function 'jump_to_image_no_args':
spl.c:103: warning: assignment makes pointer from integer without a cast
spl.c:105: warning: dereferencing type-punned pointer will break
strict-aliasing rules
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
The serial driver for iMX SOCs is continuosly changed if a
new SOC or not yet used port is used. CONFIG_SYS_<SOC>_<UART Port>
defines were used only to find the base address for the selected UART.
Instead of that, move the base address to the board configuration
file and drop all #ifdef from driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Helmut Raiger <helmut.raiger@hale.at>
CC: John Rigby <jcrigby@gmail.com>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Jason Liu <jason.hui@linaro.org>
Acked-by: Jason Liu <jason.hui@linaro.org>
Some functions were internal to the apbh dma driver, so annotate them static.
Some of the functions weren't used at all so drop them. This makes the U-Boot
binary smaller by about 1500 bytes.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This corects the warning below, obtained with my gcc 4.6 compiler.
arch/arm/cpu/armv7/mx5/libmx5.o: In function `decode_pll':
arch/arm/cpu/armv7/mx5/clock.c:94: undefined reference to `__aeabi_uldivmod'
I am not able to test this on MX5x hardware, but it does improve the
MAKEALL output for me. You may already have a similar patch, but I cannot
see it on the list.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an SPL_BOARD_INIT hook and for OMAP3 have it turn on i2c. OMAP4
doesn't need i2c enabled in SPL. Enable SPL_BOARD_INIT on devkit8000.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
Signed-off-by: Tom Rini <trini@ti.com>
This introduces 200MHz Micron parts timing information based on x-loader
to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init
logic is also based on what x-loader does in these cases. Note that
while previously u-boot would be flashed in with SW ECC in this case it
now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to
0x80100000.
Cc: Dirk Behme <dirk.behme@gmail.com>
Beagleboard rev C5, xM rev A:
Tested-by: Tom Rini <trini@ti.com>
Beagleboard xM rev C:
Tested-by: Matt Ranostay <mranostay@gmail.com>
Beagleboard rev B7, C2, xM rev B:
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
A number of boards are populated with a PoP chip for both DDR and NAND
memory. Other boards may simply use this as an easy way to identify
board revs. So we provide a function that can be called early to reset
the NAND chip and return the result of NAND_CMD_READID. All of this
code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by: Tom Rini <trini@ti.com>
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this
to provide the default 165MHz value.
Signed-off-by: Tom Rini <trini@ti.com>
This adds an MCFG macro to calculate the correct value, similar to
the ACTIMA/ACTIMB macros and adds a comment that all of the potential
values here are documented in the TRM. Then we convert the Micron
value to use this macro.
Signed-off-by: Tom Rini <trini@ti.com>
It's possible to need to call this function on the same banks multiple
times so we want to be sure that 'pos A' is cleared out again at the
end.
Signed-off-by: Tom Rini <trini@ti.com>
Since we go through the sequence to setup the SDRC timings more than
once, break this logic out into its own function and have that function
call mem_ok() to make sure the memory is usable.
Signed-off-by: Tom Rini <trini@ti.com>
We update the comment in make_cs1_contiguous() to be a little bit
more clear (it's been copy/pasted from other silicons) and then
explain in dram_init() why we need to always try this.
Note that in the previous behavior we were always calling this on
boards that never had cs1 populated anyhow so making sure we do
this always is fine and will correct things like omap3evm detecting
an invalid amount of memory (384MB).
Signed-off-by: Tom Rini <trini@ti.com>
Expand the "enable the config" comment to explain what the bit shifts
are and define out two of the magic numbers.
Signed-off-by: Tom Rini <trini@ti.com>
This patch avoids build breakage for SPLs that do not support printf.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
move the board/davinci/common/misc.c file to
arch/arm/cpu/arm926ejs/davinci/misc.c, so all
davinci boards can use this functions.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Christian Riesch <christian.riesch@omicron.at>
move struct davinci_rtc to arch/arm/include/asm/arch-davinci/hardware.h
and add RTC_KICK0R_WE, RTC_KICK1R_WE defines,
so they are global useable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
This patch replaces the pinmux configuration code in
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c by the code from
arch/arm/cpu/arm926ejs/davinci/pinmux.c.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Up to now nearly every davinci board has separate code for the
definition of pinmux configurations. This patch adds pinmux
configurations for the DA850 SoCs to the arch tree which may later
be used for all DA850 based boards.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
always do the cpu critical inits in cpu_init_crit,
and only jump to lowlevel_init, if CONFIG_SKIP_LOWLEVEL_INIT
is not defined.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Added noop implementation for dcache operations that will buzz
about missing real implementation and disable the dcache.
This fixes compilation of DaVinci EMAC driver on arm926ejs.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs
also. This patch moves common defines from arch-davinci/emac_defs.h to
drivers/net/davinci_emac.h
DaVinci specific PHY drivers hacked to include the new header. We might
want to switch to phylib in future.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
The value from TRIM is not working for some 4430 silicons.
So, override with hw team recommended value. However, for
4460 TRIM value shall be used as long as the part is trimmed
This fixes boot problem on some OMAP4430 ES2.0 Panda boards
out there.
Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
There was a typo in the EMIF driver. It went un-noticed
because it affected only when automatic detection is enabled
and even then half the memory was configured and identified
properly.
Reported-by: Rockefeller <rockefeller.lin@innocomm.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
TPS power IC is controlled using a GPIO (gpio_wk7).
This GPIO should be maintained at logic 1 always. As
such an internal pull-up on this pin will do the job,
driving the GPIO outuput is not needed. This will avoid
the need of using GPIO library in SPL and also may
save some power.
Signed-off-by: Aneesh V <aneesh@ti.com>
