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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
tegra2: Remove unneeded boot code
Since we have cache support built in we can remove Tegra's existing cache initialization code amd other related dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Albert ARIBAUD
parent
831a077f11
commit
e75119d278
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@ -82,18 +82,6 @@ _end_vect:
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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#ifdef CONFIG_TEGRA2
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/*
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* Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
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* U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
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* muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
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* to pick up its reset vector, which points here.
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*/
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.globl _armboot_start
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_armboot_start:
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.word _start
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#endif
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/*
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* These are defined in the board-specific linker script.
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*/
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@ -95,13 +95,8 @@
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#define HALT_COP_EVENT_IRQ_1 (1 << 11)
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#define HALT_COP_EVENT_FIQ_1 (1 << 9)
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/* Prototypes */
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/* Start up the tegra2 SOC */
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void tegra2_start(void);
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void uart_init(void);
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void udelay(unsigned long);
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void cold_boot(void);
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void cache_configure(void);
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/* This is the main entry into U-Boot, used by the Cortex-A9 */
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extern void _start(void);
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@ -55,14 +55,6 @@ unsigned int query_sdram_size(void)
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}
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}
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void s_init(void)
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{
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#ifndef CONFIG_ICACHE_OFF
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icache_enable();
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#endif
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invalidate_dcache();
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}
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int dram_init(void)
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{
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unsigned long rs;
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@ -24,9 +24,6 @@
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# MA 02111-1307 USA
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#
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# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI.
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PLATFORM_CPPFLAGS += -march=armv4
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# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this
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# file with compatible flags
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ifdef CONFIG_TEGRA2
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@ -26,14 +26,6 @@
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#include <config.h>
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#include <version.h>
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
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.global invalidate_dcache
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invalidate_dcache:
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mov pc, lr
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.align 5
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.global reset_cpu
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reset_cpu:
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@ -47,113 +39,3 @@ _loop_forever:
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b _loop_forever
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rstctl:
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.word PRM_RSTCTRL
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.globl lowlevel_init
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lowlevel_init:
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ldr sp, SRAM_STACK
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str ip, [sp]
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mov ip, lr
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bl s_init @ go setup pll, mux & memory
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ldr ip, [sp]
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mov lr, ip
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mov pc, lr @ back to arch calling code
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.globl startup_cpu
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startup_cpu:
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@ Initialize the AVP, clocks, and memory controller
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@ SDRAM is guaranteed to be on at this point
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ldr r0, =cold_boot @ R0 = reset vector for CPU
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bl start_cpu @ start the CPU
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@ Transfer control to the AVP code
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bl halt_avp
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@ Should never get here
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_loop_forever2:
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b _loop_forever2
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.globl cache_configure
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cache_configure:
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stmdb r13!,{r14}
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@ invalidate instruction cache
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mov r1, #0
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mcr p15, 0, r1, c7, c5, 0
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@ invalidate the i&d tlb entries
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mcr p15, 0, r1, c8, c5, 0
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mcr p15, 0, r1, c8, c6, 0
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@ enable instruction cache
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mrc p15, 0, r1, c1, c0, 0
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orr r1, r1, #(1<<12)
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mcr p15, 0, r1, c1, c0, 0
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bl enable_scu
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@ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x41
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mcr p15, 0, r0, c1, c0, 1
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@ Now flush the Dcache
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mov r0, #0
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@ 256 cache lines
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mov r1, #256
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invalidate_loop:
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add r1, r1, #-1
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mov r0, r1, lsl #5
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@ invalidate d-cache using line (way0)
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mcr p15, 0, r0, c7, c6, 2
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orr r2, r0, #(1<<30)
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@ invalidate d-cache using line (way1)
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mcr p15, 0, r2, c7, c6, 2
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orr r2, r0, #(2<<30)
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@ invalidate d-cache using line (way2)
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mcr p15, 0, r2, c7, c6, 2
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orr r2, r0, #(3<<30)
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@ invalidate d-cache using line (way3)
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mcr p15, 0, r2, c7, c6, 2
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cmp r1, #0
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bne invalidate_loop
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@ FIXME: should have ap20's L2 disabled too?
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invalidate_done:
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ldmia r13!,{pc}
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.globl cold_boot
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cold_boot:
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msr cpsr_c, #0xD3
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@ Check current processor: CPU or AVP?
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@ If CPU, go to CPU boot code, else continue on AVP path
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ldr r0, =NV_PA_PG_UP_BASE
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ldr r1, [r0]
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ldr r2, =PG_UP_TAG_AVP
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@ are we the CPU?
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ldr sp, CPU_STACK
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cmp r1, r2
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@ yep, we are the CPU
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bne _armboot_start
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@ AVP initialization follows this path
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ldr sp, AVP_STACK
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@ Init AVP and start CPU
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b startup_cpu
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@ the literal pools origin
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.ltorg
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SRAM_STACK:
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.word LOW_LEVEL_SRAM_STACK
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AVP_STACK:
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.word EARLY_AVP_STACK
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CPU_STACK:
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.word EARLY_CPU_STACK
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