Separate overo module and expansion board MUX configuration. This allows
an foreign expansion board to use the boot loader without any adaption.
It only needs to save the expansion name in the EEPROM to load a
specific device tree.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Move ethernet setup to the board_eth_init function and select
the available network devices via expansion id.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Remove unused tx_send_loop variable.
Removes duplicated get_link_status() call from the
keystone2_eth_send_packet().
The emac_gigabit_enable() is called at opening Ethernet and there is no
need to enable it on sending each packet. So remove that call
from keystone2_eth_send_packet() as well.
The calling of power/clock up functions are mostly the responsibility
of SoC/board code, so move these functions to appropriate place.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The initialization of PLLs is a part of board specific code, so
move it appropriate places.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic support for the Marvell DB-MV784MP-GP evaulation
board. This is the first board that uses the recently created
Armada XP 78460 SoC support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Additionally the SDRAM address decoding register address is not hard coded
in the C code any more. A define is introduced for this base address.
This makes is possible to use those gpio functions from other MVEBU SoC's
as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This makes is possible to use those gpio functions from other MVEBU SoC's as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Commit 155fa9af95 changed the way
to define a GPIO line, which can be used to force CS high
across multiple transactions. In order to fix sf detection
change board code to make use of board_spi_cs_gpio(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
The built-in SMSC 95xx chip doesn't know its own MAC address. Instead,
we must query it from the VC firmware; it's probably encoded in fuses
on the BCM2835.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Convert the BCM2835 GPIO driver to use driver model, and switch over
Raspberry Pi to use this, since it is the only board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Now that serial and GPIO are available for iMX.6, move cm_fx6 over as an
example.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Use gpio_request for all the gpios that are utilized by various
subsystems in cm-fx6, and refactor the relevant init functions
so that all gpios are requested during board_init(), not during
subsystem init, thus avoiding the need to manage gpio ownership
each time a subsystem is initialized.
The new division of labor is:
During board_init() muxes are setup and gpios are requested.
During subsystem init gpios are toggled.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
This converts the Tegra SPI drivers to use driver model. This is tested
on:
- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore
(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Since spi_flash.h is supposed to be the public API for SPI flash, move
private things to sf_internal.h. Also tidy up a few comment nits.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Adjust this board to use the driver model soft_spi implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.
A few device tree additions are needed to make the SPI flash available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
With driver model GPIOs must be requested before use. Make sure this is
done correctly.
(Note that the soft SPI part of universal is omitted, since this driver
is about to be replaced with a driver-model-aware version)
Signed-off-by: Simon Glass <sjg@chromium.org>
The wrong header is being included, thus requiring the code to re-declare
the generic GPIO interface in each GPIO header.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add proper initialization of GPIO pins used by software i2c.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update Apalis T30 as per the following commits
c369139234
tegra: dts: Add serial port details
461be2f96e
kconfig: remove redundant "string" type in arch and board Kconfigs
f1ef2b6233
kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Fix ASIX USB to Ethernet reset which due to the new driver model Tegra
GPIO driver changes now requires a label string to be provided
otherwise the reservation and subsequent direction/value calls will
fail.
This fixes a regression introduced by commit:
2fccd2d96b
tegra: Convert tegra GPIO driver to use driver model
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch adds board support for the Toradex Apalis T30 a computer on
module which can be used on different carrier boards.
For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.
The following functionality is working so far:
- eMMC boot and environment storage
- Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210
fixes hit mainline)
- MMC/SD cards (both 8-bit as well as 4-bit slot)
- USB client/host (dual role port as client e.g. for DFU/UMS, other two
ports as host)
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This pinmux tables currently omit any configuration for PCIe clk_req,
wake, and rst pins, which in turn causes intermittent failures in
U-Boot's PCIe support. Import an updated version of the pinmux tables
which rectifies this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Provide a public declaration of the board_spi_cs_gpio()
callback for i.MX SPI chip selects to prevent the warning
"Should it be static?" when compiling with "make C=1".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Hardware accelerated support for SHA-1 and SHA-256 has been added.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update readme file for Keystone II EVM boards to actual sources.
Also correct some typos. For now the Edison evaluation board is
added, README for K2E is mostly the same, so update README to
contain information also for K2E evm. Rename file to README as
it contains information for all keystone evm boards.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Tom Rini <trini@ti.com>
fix broken SPI access by adding/activating BOARD_EARLY_INIT_F
functionality and calling spi_init_f() from there.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
Fix typo of commit d4e53f063d.
i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1.
It's value after reset is 0x00100001.
In order to clear bit 0, original code write 0xfffffffe to
CONTROL_PROG_IO1 and toggle almost all default values.
Original code affect following:
* disable i2c1 pullup resisters
* increase far end load setting for many modules
* setup invalid SC/LB combination
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
CC: Tom Rini <trini@ti.com>
CC: Steve Kipisz <s-kipisz2@ti.com>
This board has been orphaned for more than 6 months.
It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().
Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Add default eeprom bus setting.
This addresses the trimslice compile error that was introduced
with the addition of this setting.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
In order for the gmac nic to work reliable on the Bananapi, we need to set
bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register
(0x01c20164) to 3.
Without this about 9 out of 10 ethernet packets get lost, with this setting
there is no packet loss.
So far setting these bits is only necessary on the Bananapi, so this commit
solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we
need to do something similar for other boards, we can create a specific
CONFIG_FOO option for this then.
Reported-by: Karsten Merker <merker@debian.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Zoltan HERPAI <wigyori@openwrt.org>
Tested-by: Tony Zhang <tony.zhang@lemaker.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This change fixes suspend/resume issue in the kernel caused
by the wrong 'aclk_cores' clock value expected by the kernel.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The email address of Rajeshwari Shinde <rajeshwari.s@samsung.com>
is not working.
This commit gives Akshay the maintainership of Snow and
SMDK5420 boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock
periods that were doing nothing.
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>
The HPD pin and RX_SENSE registers have proven to be less reliable
than using I2C on the EDID pins for detection of an HDMI monitor.
In particular, when the HDMI output is reset through a "reboot"
cycle, the detect_hdmi() routine often bounces, resulting in
a failure to detect a connected monitor.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for WVGA (800x480) panels using VESA GTF timings over
LVDS.
No auto-detection is supported, so you must configure this panel
manually through the 'panel' environment variable:
U-Boot > setenv panel svga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for an Ampire 1024x600 LVDS panel with integrated Ilitek
capacitive touch screen.
Auto-detection is enabled, so no explicit configuration is needed.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for 800x600 18-bit RGB displays using VESA GTF timings.
No auto-detection is supported, so you must configure this panel
manually through the 'panel' environment variable:
U-Boot > setenv panel svga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for the Touch Revolution Fusion7 display: 800x480 RGB
with a custom F0710A resistive touch controller.
Auto-detection of this panel is supported so no configuration is
required.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This patch adds support for LVDS WXGA displays that use the SPWG encoding
standard instead of JEIDA.
No auto-detection is enabled and you must explicitly set the 'panel'
environment variable:
U-Boot > setenv panel LDB-WXGA-S
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for LG 9.7" LVDS panel (1024x768) with integrated eGalax
touch screen.
Note that this panel differs only slightly from the Hannstar XGA panel
(margins).
No auto-detection is available because it shares the same touch controller
as the Hannstar-XGA display, so you'll need to configure it through the
'panel' environment variable:
U-Boot > setenv panel LG-9.7
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for a 1/4 VGA panel with a 24-bit RGB interface.
No auto-detection is enabled, so you must configure the 'panel'
environment variable to use this display:
U-Boot > setenv panel qvga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for Boundary Devices 7" and 10.1" 1280x800 displays with
integrated FocalTech ft5x06 10-point touch controller.
Because they share the touch controller with the 1024x600 displays,
auto-detection is disabled and you must explicitly set the 'panel'
environment variable:
U-Boot > setenv panel LDB-WXGA
U-Boot > saveenv && reset
Signed-off-by: Robert Winkler <robert.winkler@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Include declarations of board_ehci callbacks to prevent compiler warnings
and enforce function prototypes.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Testing shows that the Micrel PHY may not be completely out
of reset if accessed immediately.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Declare locally-used data structures and functions as
static and pull in header files to prevent compiler warnings
of "Should it be static?" when building with "make C=1".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Configure CLKO outputs for SGTL5000, CSI camera.
The sys_mclk output for the SGTL500 in particular prevents
Windows CE from properly driving audio.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Ensure that cameras and USB OTG power are in a stable (reset)
state at reset by configuring their pads and toggling GPIOs.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Pads SD2_CLK/CMD/DAT0-3 are connected to an SDIO WiFi device on
Nitrogen and unconnected on BD-SL-i.MX6 (sabre lite).
Configure them as SDIO pins to prevent them from being in a state
that confuses the WiFi part.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The same logic applies to both SD card slots, only with different
GPIOs and the code should make that easier to see.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Several customers have asked to leave the display quiet during
boot, so allow the user to express this request by the presence
of environment variable "novideo".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cosmetic change to the checkboard() function output. Align the
output with the rest of initial output produced by U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The bi_boot_params must point to offset 0x100 in DRAM. Make it so.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
For more details see README.
Changes v1 > v2
- make use of enable_cspi_clock(..)
- fix usage of OUTPUT_40OHM define
- added README
Changes v2 > v3
- improve spelling in README
- added own copy of mx6q_4x_mt41j128.cfg
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Update DDR calibration settings based on a larger test set.
The initial values were gathered on a small number of boards,
and have been found to fail on some boards under load.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Zeroing GD in board_init_f() is not needed any more. As its now done in
crt0.S. The patch that clears the GD in crt0.S is this one:
aae2aef9 [arm: Set up global data before board_init_f()] from Simon.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.
Signed-off-by: Ye.Li <B37916@freescale.com>
This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
Signed-off-by: Ye.Li <B37916@freescale.com>
Add fine-tuning for the DRAM configuration according to the DRAM chip
datasheet. THis configuration applies to both Hynix HY5DU12622DTP and
Samsung K5H511538J-D43 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Enable the power to the USB port only when the USB port is really needed.
Do not enable the power unconditionally.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.
Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
