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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Tom Rini 2014-10-07 07:38:39 -04:00
commit dd0204e48d
84 changed files with 5675 additions and 74 deletions
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9
MAINTAINERS
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@ -149,6 +149,15 @@ F: arch/arm/include/asm/arch-davinci/
F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
ARM UNIPHIER
M: Masahiro Yamada <yamada.m@jp.panasonic.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/cpu/armv7/uniphier/
F: arch/arm/include/asm/arch-uniphier/
F: configs/ph1_*_defconfig
F: drivers/serial/serial_uniphier.c
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>
S: Maintained

5
arch/arm/Kconfig
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@ -521,6 +521,9 @@ config TARGET_COLIBRI_PXA270
config TARGET_JORNADA
bool "Support jornada"
config ARCH_UNIPHIER
bool "Panasonic UniPhier platform"
endchoice
source "arch/arm/cpu/armv8/Kconfig"
@ -549,6 +552,8 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig"
source "arch/arm/cpu/armv7/tegra-common/Kconfig"
source "arch/arm/cpu/armv7/uniphier/Kconfig"
source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
source "arch/arm/cpu/armv7/zynq/Kconfig"

32
arch/arm/cpu/armv7/uniphier/Kconfig Normal file
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@ -0,0 +1,32 @@
menu "Panasonic UniPhier platform"
depends on ARCH_UNIPHIER
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "uniphier"
config SYS_CONFIG_NAME
string
default "ph1_pro4" if MACH_PH1_PRO4
default "ph1_ld4" if MACH_PH1_LD4
default "ph1_sld8" if MACH_PH1_SLD8
choice
prompt "UniPhier SoC select"
config MACH_PH1_PRO4
bool "PH1-Pro4"
config MACH_PH1_LD4
bool "PH1-LD4"
config MACH_PH1_SLD8
bool "PH1-sLD8"
endchoice
endmenu

23
arch/arm/cpu/armv7/uniphier/Makefile Normal file
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@ -0,0 +1,23 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += timer.o
obj-y += reset.o
obj-y += cache_uniphier.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/

32
arch/arm/cpu/armv7/uniphier/board_common.c Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
led_write(U, B, O, O);
return 0;
}
#if CONFIG_NR_DRAM_BANKS >= 2
void dram_init_banksize(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
}
#endif

91
arch/arm/cpu/armv7/uniphier/board_late_init.c Normal file
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@ -0,0 +1,91 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <nand.h>
#include <asm/io.h>
#include <../drivers/mtd/nand/denali.h>
static void nand_denali_wp_disable(void)
{
#ifdef CONFIG_NAND_DENALI
/*
* Since the boot rom enables the write protection for NAND boot mode,
* it must be disabled somewhere for "nand write", "nand erase", etc.
* The workaround is here to not disturb the Denali NAND controller
* driver just for a really SoC-specific thing.
*/
void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
#endif
}
static void nand_denali_fixup(void)
{
#if defined(CONFIG_NAND_DENALI) && \
(defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
/*
* The Denali NAND controller on some of UniPhier SoCs does not
* automatically query the device parameters. For those SoCs,
* some registers must be set after the device is probed.
*/
void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
struct mtd_info *mtd;
struct nand_chip *chip;
if (nand_curr_device < 0 ||
nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
/* NAND was not detected. Just return. */
return;
}
mtd = &nand_info[nand_curr_device];
chip = mtd->priv;
writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
writel(0, denali_reg + DEVICE_WIDTH);
writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
writel(1, denali_reg + DEVICES_CONNECTED);
/*
* chip->scan_bbt in nand_scan_tail() has been skipped.
* It should be done in here.
*/
chip->scan_bbt(mtd);
#endif
}
int board_late_init(void)
{
puts("MODE: ");
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
nand_denali_fixup();
break;
case BOOT_DEVICE_NAND:
printf("NAND Boot\n");
setenv("bootmode", "nandboot");
nand_denali_wp_disable();
break;
case BOOT_DEVICE_NOR:
printf("NOR Boot\n");
setenv("bootmode", "norboot");
nand_denali_fixup();
break;
default:
printf("Unsupported Boot Mode\n");
return -1;
}
return 0;
}

154
arch/arm/cpu/armv7/uniphier/cache_uniphier.c Normal file
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@ -0,0 +1,154 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7.h>
#include <asm/arch/ssc-regs.h>
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)
{
/* try until the command is successfully set */
do {
writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(SSCOLPQS) != SSCOLPQS_EF)
;
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
readl(SSCOPE); /* need a read back to confirm */
}
void v7_outer_cache_flush_all(void)
{
uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
}
void v7_outer_cache_inval_all(void)
{
uniphier_cache_maint_all(SSCOQM_CM_INV);
}
static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
{
/* try until the command is successfully set */
do {
writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
writel(start, SSCOQAD);
writel(size, SSCOQSZ);
} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(SSCOLPQS) != SSCOLPQS_EF)
;
/* clear the complete notification flag */
writel(SSCOLPQS_EF, SSCOLPQS);
}
static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
{
u32 size;
/*
* If start address is not aligned to cache-line,
* do cache operation for the first cache-line
*/
start = start & ~(SSC_LINE_SIZE - 1);
if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
}
/*
* If end address is not aligned to cache-line,
* do cache operation for the last cache-line
*/
size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
while (size) {
u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
SSC_RANGE_OP_MAX_SIZE : size;
__uniphier_cache_maint_range(start, chunk_size, operation);
start += chunk_size;
size -= chunk_size;
}
writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
readl(SSCOPE); /* need a read back to confirm */
}
void v7_outer_cache_flush_range(u32 start, u32 end)
{
uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
}
void v7_outer_cache_inval_range(u32 start, u32 end)
{
uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
}
void v7_outer_cache_enable(void)
{
u32 tmp;
tmp = readl(SSCC);
tmp |= SSCC_ON;
writel(tmp, SSCC);
}
#endif
void v7_outer_cache_disable(void)
{
u32 tmp;
tmp = readl(SSCC);
tmp &= ~SSCC_ON;
writel(tmp, SSCC);
}
void wakeup_secondary(void);
void enable_caches(void)
{
uint32_t reg;
#ifdef CONFIG_UNIPHIER_SMP
/*
* The secondary CPU must move to DDR,
* before L2 disable.
* On SPL, the Page Table is located on the L2.
*/
wakeup_secondary();
#endif
/*
* UniPhier SoCs must use L2 cache for init stack pointer.
* We disable L2 and L1 in this order.
* If CONFIG_SYS_DCACHE_OFF is not defined,
* caches are enabled again with a new page table.
*/
/* L2 disable */
v7_outer_cache_disable();
/* L1 disable */
reg = get_cr();
reg &= ~(CR_C | CR_M);
set_cr(reg);
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}

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arch/arm/cpu/armv7/uniphier/cmd_pinmon.c Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/boot-device.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct boot_device_info *table;
u32 mode_sel, n = 0;
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (table = boot_device_table; strlen(table->info); table++) {
printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n,
table->info);
n++;
}
return 0;
}
U_BOOT_CMD(
pinmon, 1, 1, do_pinmon,
"pin monitor",
""
);

59
arch/arm/cpu/armv7/uniphier/cpu_info.c Normal file
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@ -0,0 +1,59 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
int print_cpuinfo(void)
{
u32 revision, type, model, rev, required_model = 1, required_rev = 1;
revision = readl(SG_REVISION);
type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
puts("CPU: ");
switch (type) {
case 0x25:
puts("PH1-sLD3 (MN2WS0220)");
required_model = 2;
break;
case 0x26:
puts("PH1-LD4 (MN2WS0250)");
required_rev = 2;
break;
case 0x28:
puts("PH1-Pro4 (MN2WS0230)");
break;
case 0x29:
puts("PH1-sLD8 (MN2WS0270)");
break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
return -1;
}
if (model > 1)
printf(" model %d", model);
printf(" (rev. %d)\n", rev);
if (model < required_model) {
printf("Sorry, this model is not supported.\n");
printf("Required model is %d.", required_model);
return -1;
} else if (rev < required_rev) {
printf("Sorry, this revision is not supported.\n");
printf("Required revision is %d.", required_rev);
return -1;
}
return 0;
}

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arch/arm/cpu/armv7/uniphier/dram_init.c Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
int umc_init(void);
void enable_dpll_ssc(void);
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
led_write(B, 4, , );
{
int res;
res = umc_init();
if (res < 0)
return res;
}
led_write(B, 5, , );
enable_dpll_ssc();
#endif
led_write(B, 6, , );
return 0;
}

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arch/arm/cpu/armv7/uniphier/init_page_table.c Normal file
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159
arch/arm/cpu/armv7/uniphier/lowlevel_init.S Normal file
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@ -0,0 +1,159 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/arch/led.h>
#include <asm/arch/arm-mpcore.h>
#include <asm/arch/sbc-regs.h>
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
/*
* The UniPhier Boot ROM loads SPL code to the L2 cache.
* But CPUs can only do instruction fetch now because start.S has
* cleared C and M bits.
* First we need to turn on MMU and Dcache again to get back
* data access to L2.
*/
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
/*
* Now we are using the page table embedded in the Boot ROM.
* It is not handy since it is not a straight mapped table for sLD3.
* What we need to do next is to switch over to the page table in SPL.
*/
ldr r3, =init_page_table @ page table must be 16KB aligned
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
bl enable_mmu
#ifdef CONFIG_UNIPHIER_SMP
/*
* ACTLR (Auxiliary Control Register) for Cortex-A9
* bit[9] Parity on
* bit[8] Alloc in one way
* bit[7] EXCL (Exclusive cache bit)
* bit[6] SMP
* bit[3] Write full line of zeros mode
* bit[2] L1 Prefetch enable
* bit[1] L2 prefetch enable
* bit[0] FW (Cache and TLB maintenance broadcast)
*/
mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
orr r0, r0, #0x41 @ enable SMP, FW bit
mcr p15, 0, r0, c1, c0, 1
/* branch by CPU ID */
mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
and r0, r0, #0x3
cmp r0, #0x0
beq primary_cpu
ldr r1, =ROM_BOOT_ROMRSV2
mov r0, #0
str r0, [r1]
0: wfe
ldr r0, [r1]
cmp r0, #0
beq 0b
bx r0 @ r0: entry point of U-Boot main for the secondary CPU
primary_cpu:
ldr r1, =ROM_BOOT_ROMRSV2
ldr r0, =_start @ entry for the secondary CPU
str r0, [r1]
ldr r0, [r1] @ make sure str is complete before sev
sev @ kick the sedoncary CPU
mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
bfc r1, #0, #13 @ clear bit 12-0
mov r0, #-1
str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
mov r0, #1 @ SCU enable
str r0, [r1, #SCU_CTRL] @ SCU Control Register
#endif
bl setup_init_ram @ RAM area for temporary stack pointer
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
ENTRY(enable_mmu)
mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
bic r0, r0, #0x37
orr r0, r0, #0x20 @ disable TTBR1
mcr p15, 0, r0, c2, c0, 2
orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
mcr p15, 0, r0, c2, c0, 0 @ TTBR0
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mov r0, #-1 @ manager for all domains (No permission check)
mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
dsb
isb
/*
* MMU on:
* TLBs was already invalidated in "../start.S"
* So, we don't need to invalidate it here.
*/
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
ENDPROC(enable_mmu)
#include <asm/arch/ssc-regs.h>
#define BOOT_RAM_SIZE (SSC_WAY_SIZE)
#define BOOT_WAY_BITS (0x00000100) /* way 8 */
ENTRY(setup_init_ram)
/*
* Touch to zero for the boot way
*/
0:
/*
* set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
*/
ldr r0, = 0x00408006 @ touch to zero with address range
ldr r1, = SSCOQM
str r0, [r1]
ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
ldr r1, = SSCOQAD
str r0, [r1]
ldr r0, = BOOT_RAM_SIZE
ldr r1, = SSCOQSZ
str r0, [r1]
ldr r0, = BOOT_WAY_BITS
ldr r1, = SSCOQWN
str r0, [r1]
ldr r1, = SSCOPPQSEF
ldr r0, [r1]
cmp r0, #0 @ check if the command is successfully set
bne 0b @ try again if an error occurres
ldr r1, = SSCOLPQS
1:
ldr r0, [r1]
cmp r0, #0x4
bne 1b @ wait until the operation is completed
str r0, [r1] @ clear the complete notification flag
mov pc, lr
ENDPROC(setup_init_ram)

10
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile Normal file
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@ -0,0 +1,10 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
umc_init.o

33
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/bcu-regs.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
void bcu_init(void)
{
int shift;
writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
}

16
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-LD4 Board\n");
return check_support_card();
}

42
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void bcu_init(void);
void sbc_init(void);
void sg_init(void);
void pll_init(void);
void pin_init(void);
void clkrst_init(void);
int board_postclk_init(void)
{
bcu_init();
sbc_init();
sg_init();
pll_init();
uniphier_board_init();
led_write(B, 1, , );
clkrst_init();
led_write(B, 2, , );
pin_init();
led_write(B, 3, , );
return 0;
}

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arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c Normal file
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#include "../ph1-pro4/boot-mode.c"

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arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

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arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void pin_init(void)
{
u32 tmp;
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
#endif
tmp = readl(SG_IECTRL);
tmp |= 0x41;
writel(tmp, SG_IECTRL);
}

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arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
{
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x000f0000;
#if CONFIG_DDR_FREQ == 1600
tmp |= 0x000c0000;
#elif CONFIG_DDR_FREQ == 1333
tmp |= 0x000d0000;
#else
# error "Unknown frequency"
#endif
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~SC_DPLLCTRL_SSC_RATE;
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
tmp = readl(SC_UPLLCTRL);
tmp &= ~0x18000000;
writel(tmp, SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp &= ~0x07ffffff;
tmp |= 0x0228f5c0;
} else {
/* AXO: default 24.576MHz */
tmp &= ~0x07ffffff;
tmp |= 0x02328000;
}
}
writel(tmp, SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
writel(tmp, SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
void pll_init(void)
{
dpll_init();
upll_init();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 10 usec in upll_init() and vpll_init()
* so 20 usec can be saved here.
*/
udelay(480);
}

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arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c Normal file
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#include "../ph1-pro4/pll_spectrum.c"

44
arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
#if !defined(CONFIG_SPL_BUILD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
#if !defined(CONFIG_SPL_BUILD)
/* enable access to sub memory when boot swap is on */
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
#endif
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}

28
arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

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arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_FRCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
if (freq == 1333) {
writel(0x45990b11, dramcont + UMC_CMDCTLA);
writel(0x16958924, dramcont + UMC_CMDCTLB);
writel(0x5101046A, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x27028B0A, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x38028B0A, dramcont + UMC_INITCTLB);
writel(0x000FF0FF, dramcont + UMC_INITCTLC);
writel(0x00000b51, dramcont + UMC_DRMMR0);
} else if (freq == 1600) {
writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
writel(0x5101387F, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x2F030D3F, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x43030D3F, dramcont + UMC_INITCTLB);
writel(0x00FF00FF, dramcont + UMC_INITCTLC);
writel(0x00000d71, dramcont + UMC_DRMMR0);
}
writel(0x00000006, dramcont + UMC_DRMMR1);
if (freq == 1333)
writel(0x00000290, dramcont + UMC_DRMMR2);
else if (freq == 1600)
writel(0x00000298, dramcont + UMC_DRMMR2);
writel(0x00000800, dramcont + UMC_DRMMR3);
if (freq == 1333) {
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
else if (size == 2)
writel(0x00350512, dramcont + UMC_SPCCTLA);
writel(0x00ff0006, dramcont + UMC_SPCCTLB);
writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
} else if (freq == 1600) {
if (size == 1)
writel(0x002B0617, dramcont + UMC_SPCCTLA);
else if (size == 2)
writel(0x003F0617, dramcont + UMC_SPCCTLA);
writel(0x00ff0008, dramcont + UMC_SPCCTLB);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
}
writel(0x04060806, dramcont + UMC_WDATACTL_D0);
writel(0x04a02000, dramcont + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dramcont + UMC_DCCGCTL);
writel(0x00000003, dramcont + 0x7000);
writel(0x0000000f, dramcont + 0x8000);
writel(0x000000c3, dramcont + 0x8004);
writel(0x00000071, dramcont + 0x8008);
writel(0x0000003b, dramcont + UMC_DICGCTLA);
writel(0x020a0808, dramcont + UMC_DICGCTLB);
writel(0x00000004, dramcont + UMC_FLOWCTLG);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
writel(0x00200000, dramcont + UMC_FLOWCTLB);
writel(0x00004444, dramcont + UMC_FLOWCTLC);
writel(0x200a0a00, dramcont + UMC_SPCSETB);
writel(0x00000000, dramcont + UMC_SPCSETD);
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
umc_dram_init_poll(dramcont0);
umc_dram_init_poll(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
umc_start_ssif(ssif_base);
return 0;
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}
#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
#error Unsupported DDR Frequency.
#endif
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
/* OK */
#else
#error Unsupported DDR configuration.
#endif

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arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile Normal file
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#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
umc_init.o

16
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c Normal file
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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-Pro4 Board\n");
return check_support_card();
}

39
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c Normal file
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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void sbc_init(void);
void sg_init(void);
void pll_init(void);
void pin_init(void);
void clkrst_init(void);
int board_postclk_init(void)
{
sbc_init();
sg_init();
pll_init();
uniphier_board_init();
led_write(B, 1, , );
clkrst_init();
led_write(B, 2, , );
pin_init();
led_write(B, 3, , );
return 0;
}

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arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c Normal file
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/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/boot-device.h>
#include <asm/arch/sg-regs.h>
#include <asm/arch/sbc-regs.h>
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, ""}
};
u32 get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 spl_boot_device(void)
{
u32 boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}

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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

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arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
sg_set_pinsel(48, 0); /* NFALE -> NFALE */
sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
#endif
writel(1, SG_LOADPINCTRL);
}

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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
{
u32 tmp;
/*
* Set Frequency
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT ( DPLLCTRL.bit[29:20] )
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~(0x000f0000);
#if CONFIG_DDR_FREQ == 1600
tmp |= 0x000c0000;
#elif CONFIG_DDR_FREQ == 1333
tmp |= 0x000d0000;
#else
# error "Unsupported frequency"
#endif
/*
* Set Moduration rate
* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
*/
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~0x00008000;
#else
tmp |= 0x00008000;
#endif
writel(tmp, SC_DPLLCTRL);
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
}
void stop_mpll(void)
{
u32 tmp;
tmp = readl(SC_MPLLOSCCTL);
if (!(tmp & SC_MPLLOSCCTL_MPLLST))
return; /* already stopped */
tmp &= ~SC_MPLLOSCCTL_MPLLEN;
writel(tmp, SC_MPLLOSCCTL);
while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
;
}
void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
/* Set VPLL27A & VPLL27B */
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
#if defined(CONFIG_MACH_PH1_PRO4)
/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
return;
#endif
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Unset VPLA_K_LD and VPLB_K_LD bit */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set VPLA_M and VPLB_M to 0x20 */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
/* Set VPLA_K and VPLB_K for AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* wait 1 usec */
udelay(1);
/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Unset VPLA_SNRST and VPLB_SNRST bit */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
void pll_init(void)
{
dpll_init();
stop_mpll();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 1 usec in vpll_init() so 1 usec can be saved here.
*/
udelay(499);
}

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arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void enable_dpll_ssc(void)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
}

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arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
if (readl(SBBASE0) & 0x1) {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x3effffff: memory bank (31MB)
* 0x03f00000-0x3fffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
} else {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
#if !defined(CONFIG_SPL_BUILD)
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
#endif
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
}

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arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000001, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x07ffffff, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010100, ssif_base + UMC_HDMCHSEL);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DVCCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_HDMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_HDDRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_GIORST);
writel(0x00000001, ssif_base + UMC_HD2RST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_DVCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_VPERST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
writel(0x5101387f, dramcont + UMC_INITCTLA);
writel(0x43030d3f, dramcont + UMC_INITCTLB);
writel(0x00ff00ff, dramcont + UMC_INITCTLC);
writel(0x00000d71, dramcont + UMC_DRMMR0);
writel(0x00000006, dramcont + UMC_DRMMR1);
writel(0x00000298, dramcont + UMC_DRMMR2);
writel(0x00000000, dramcont + UMC_DRMMR3);
writel(0x003f0617, dramcont + UMC_SPCCTLA);
writel(0x00ff0008, dramcont + UMC_SPCCTLB);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
writel(0x04060802, dramcont + UMC_WDATACTL_D0);
writel(0x04060802, dramcont + UMC_WDATACTL_D1);
writel(0x04a02000, dramcont + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dramcont + UMC_DCCGCTL);
writel(0x0000000f, dramcont + 0x7000);
writel(0x0000000f, dramcont + 0x8000);
writel(0x000000c3, dramcont + 0x8004);
writel(0x00000071, dramcont + 0x8008);
writel(0x00000004, dramcont + UMC_FLOWCTLG);
writel(0x00000000, dramcont + 0x0060);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
writel(0x00200000, dramcont + UMC_FLOWCTLB);
writel(0x00004444, dramcont + UMC_FLOWCTLC);
writel(0x200a0a00, dramcont + UMC_SPCSETB);
writel(0x00010000, dramcont + UMC_SPCSETD);
writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
umc_dram_init_poll(dramcont0);
umc_dram_init_poll(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
umc_start_ssif(ssif_base);
return 0;
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}
#if CONFIG_DDR_FREQ != 1600
#error Unsupported DDR frequency.
#endif
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
(CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
/* OK */
#else
#error Unsupported DDR configuration.
#endif

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#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += boot-mode.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
umc_init.o

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arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c Normal file
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#include "../ph1-ld4/bcu_init.c"

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arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c Normal file
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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-sLD8 Board\n");
return check_support_card();
}

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c Normal file
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#include "../ph1-ld4/board_postclk_init.c"

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c Normal file
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#include "../ph1-pro4/boot-mode.c"

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arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

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arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void pin_init(void)
{
/* Comment format: PAD Name -> Function Name */
#ifdef CONFIG_UNIPHIER_SERIAL
sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
#endif
}

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arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
void dpll_init(void)
{
u32 tmp;
/*
* Set DPLL SSC parameters for DPLLCTRL3
* [23] DIVN_TEST 0x1
* [22:16] DIVN 0x50
* [10] FREFSEL_TEST 0x1
* [9:8] FREFSEL 0x2
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
tmp = readl(SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
writel(tmp, SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
* <-1%> <-2%>
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef CONFIG_DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
writel(tmp, SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
* [31:29] SSC_STEP 0
* [27] SSC_REG_REF 1
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
tmp = readl(SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
tmp = readl(SC_UPLLCTRL);
tmp &= ~0x18000000;
writel(tmp, SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp &= ~0x07ffffff;
tmp |= 0x0228f5c0;
} else {
/* AXO: default 24.576MHz */
tmp &= ~0x07ffffff;
tmp |= 0x02328000;
}
}
writel(tmp, SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
writel(tmp, SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= 0x00000001;
writel(tmp, SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
writel(tmp, SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
writel(tmp, SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
tmp = readl(SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
writel(tmp, SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
tmp = readl(SC_VPLL27ACTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL3);
tmp = readl(SC_VPLL27BCTRL3);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
tmp = readl(SC_VPLL27ACTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27ACTRL2);
tmp = readl(SC_VPLL27BCTRL2);
tmp |= 0x10000000;
writel(tmp, SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
tmp = readl(SC_VPLL27ACTRL);
tmp &= ~0x00000001;
writel(tmp, SC_VPLL27ACTRL);
tmp = readl(SC_VPLL27BCTRL);
tmp |= ~0x00000001;
writel(tmp, SC_VPLL27BCTRL);
}
void pll_init(void)
{
dpll_init();
upll_init();
vpll_init();
/*
* Wait 500 usec until dpll get stable
* We wait 10 usec in upll_init() and vpll_init()
* so 20 usec can be saved here.
*/
udelay(480);
}

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c Normal file
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#include "../ph1-ld4/pll_spectrum.c"

51
arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
#if !defined(CONFIG_SPL_BUILD)
/* XECS0 : dummy */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS1 : boot memory (always boot swap = on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS4 : sub memory */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
/* XECS5 : peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
/* base address regsiters */
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0900bfff, SBBASE1); /* dummy */
writel(0x0400bc01, SBBASE4); /* sub memory */
writel(0x0800bf01, SBBASE5); /* peripherals */
sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
/* dummy read to assure write process */
readl(SG_PINCTRL(33));
}

1
arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c Normal file
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#include "../ph1-ld4/sg_init.c"

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arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
writel(0x000fffcf, ssif_base + 0x0000c008);
writel(0x00000001, ssif_base + 0x0000b000);
writel(0x00000001, ssif_base + 0x0000c000);
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
writel(0x00000001, ssif_base + UMC_CPURST);
writel(0x00000001, ssif_base + UMC_IDSRST);
writel(0x00000001, ssif_base + UMC_IXMRST);
writel(0x00000001, ssif_base + UMC_MDMRST);
writel(0x00000001, ssif_base + UMC_MDDRST);
writel(0x00000001, ssif_base + UMC_SIORST);
writel(0x00000001, ssif_base + UMC_VIORST);
writel(0x00000001, ssif_base + UMC_FRCRST);
writel(0x00000001, ssif_base + UMC_RGLRST);
writel(0x00000001, ssif_base + UMC_AIORST);
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
#ifdef CONFIG_DDR_STANDARD
writel(0x55990b11, dramcont + UMC_CMDCTLA);
writel(0x16958944, dramcont + UMC_CMDCTLB);
#else
writel(0x45990b11, dramcont + UMC_CMDCTLA);
writel(0x16958924, dramcont + UMC_CMDCTLB);
#endif
writel(0x5101046A, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x27028B0A, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x38028B0A, dramcont + UMC_INITCTLB);
writel(0x00FF00FF, dramcont + UMC_INITCTLC);
writel(0x00000b51, dramcont + UMC_DRMMR0);
writel(0x00000006, dramcont + UMC_DRMMR1);
writel(0x00000290, dramcont + UMC_DRMMR2);
#ifdef CONFIG_DDR_STANDARD
writel(0x00000000, dramcont + UMC_DRMMR3);
#else
writel(0x00000800, dramcont + UMC_DRMMR3);
#endif
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
else if (size == 2)
writel(0x00350512, dramcont + UMC_SPCCTLA);
writel(0x00ff0006, dramcont + UMC_SPCCTLB);
writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
writel(0x04060806, dramcont + UMC_WDATACTL_D0);
writel(0x04a02000, dramcont + UMC_DATASET);
writel(0x00000000, ca_base + 0x2300);
writel(0x00400020, dramcont + UMC_DCCGCTL);
writel(0x00000003, dramcont + 0x7000);
writel(0x0000004f, dramcont + 0x8000);
writel(0x000000c3, dramcont + 0x8004);
writel(0x00000077, dramcont + 0x8008);
writel(0x0000003b, dramcont + UMC_DICGCTLA);
writel(0x020a0808, dramcont + UMC_DICGCTLB);
writel(0x00000004, dramcont + UMC_FLOWCTLG);
writel(0x80000201, ca_base + 0xc20);
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
writel(0x00200000, dramcont + UMC_FLOWCTLB);
writel(0x00004444, dramcont + UMC_FLOWCTLC);
writel(0x200a0a00, dramcont + UMC_SPCSETB);
writel(0x00000000, dramcont + UMC_SPCSETD);
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
umc_dram_init_start(dramcont0);
umc_dram_init_start(dramcont1);
umc_dram_init_poll(dramcont0);
umc_dram_init_poll(dramcont1);
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
umc_start_ssif(ssif_base);
return 0;
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}
#if CONFIG_DDR_FREQ != 1333
#error Unsupported DDR frequency.
#endif
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
/* OK */
#else
#error Unsupported DDR configuration.
#endif

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arch/arm/cpu/armv7/uniphier/reset.c Normal file
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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/board.h>
void reset_cpu(unsigned long ignored)
{
u32 tmp;
uniphier_board_reset();
writel(5, SC_IRQTIMSET); /* default value */
tmp = readl(SC_SLFRSTSEL);
tmp &= ~0x3; /* mask [1:0] */
tmp |= 0x0; /* XRST reboot */
writel(tmp, SC_SLFRSTSEL);
tmp = readl(SC_SLFRSTCTL);
tmp |= 0x1;
writel(tmp, SC_SLFRSTCTL);
}

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arch/arm/cpu/armv7/uniphier/smp.S Normal file
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/*
* Copyright (C) 2013 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/arch/led.h>
#include <asm/arch/sbc-regs.h>
/* Entry point of U-Boot main program for the secondary CPU */
LENTRY(secondary_entry)
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
dsb
led_write(C,0,,)
ldr r1, =ROM_BOOT_ROMRSV2
mov r0, #0
str r0, [r1]
0: wfe
ldr r4, [r1] @ r4: entry point for secondary CPUs
cmp r4, #0
beq 0b
led_write(C, P, U, 1)
bx r4 @ secondary CPUs jump to linux
ENDPROC(secondary_entry)
ENTRY(wakeup_secondary)
ldr r1, =ROM_BOOT_ROMRSV2
0: ldr r0, [r1]
cmp r0, #0
bne 0b
/* set entry address and send event to the secondary CPU */
ldr r0, =secondary_entry
str r0, [r1]
ldr r0, [r1] @ make sure store is complete
mov r0, #0x100
0: subs r0, r0, #1 @ I don't know the reason, but without this wait
bne 0b @ fails to wake up the secondary CPU
sev
/* wait until the secondary CPU reach to secondary_entry */
0: ldr r0, [r1]
cmp r0, #0
bne 0b
bx lr
ENDPROC(wakeup_secondary)

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arch/arm/cpu/armv7/uniphier/spl.c Normal file
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/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
void spl_board_init(void)
{
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init();
#endif
dram_init();
}

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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/board.h>
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
#define PFC_MICRO_SUPPORT_CARD_RESET \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
#define PFC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
/*
* 0: reset deassert, 1: reset
*
* bit[0]: LAN, I2C, LED
* bit[1]: UART
*/
void support_card_reset_deassert(void)
{
writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
}
void support_card_reset(void)
{
writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
return 0;
}
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
#define DCC_MICRO_SUPPORT_CARD_REVISION \
((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
void support_card_reset_deassert(void)
{
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
void support_card_reset(void)
{
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
}
static int support_card_show_revision(void)
{
u32 revision;
revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
if (revision >= 0x67) {
printf("(DCC CPLD version 3.%d.%d)\n",
revision >> 4, revision & 0xf);
return 0;
} else {
printf("(DCC CPLD unknown version)\n");
return -1;
}
}
#endif
void support_card_init(void)
{
/*
* After power on, we need to keep the LAN controller in reset state
* for a while. (200 usec)
* Fortunatelly, enough wait time is already inserted in pll_init()
* function. So we do not have to wait here.
*/
support_card_reset_deassert();
}
int check_support_card(void)
{
printf("SC: Micro Support Card ");
return support_card_show_revision();
}
#if defined(CONFIG_SMC911X)
#include <netdev.h>
int board_eth_init(bd_t *bis)
{
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
#include <mtd/cfi_flash.h>
#if CONFIG_SYS_MAX_FLASH_BANKS > 1
static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
CONFIG_SYS_FLASH_BANKS_LIST;
phys_addr_t cfi_flash_bank_addr(int i)
{
return flash_banks_list[i];
}
#endif
int mem_is_flash(phys_addr_t base)
{
const int loop = 128;
u32 *scratch_addr;
u32 saved_value;
int ret = 1;
int i;
scratch_addr = map_physmem(base + 0x01e00000,
sizeof(u32) * loop, MAP_NOCACHE);
for (i = 0; i < loop; i++, scratch_addr++) {
saved_value = readl(scratch_addr);
writel(~saved_value, scratch_addr);
if (readl(scratch_addr) != saved_value) {
/* We assume no memory or SRAM here. */
writel(saved_value, scratch_addr);
ret = 0;
break;
}
}
unmap_physmem(scratch_addr, MAP_NOCACHE);
return ret;
}
int board_flash_wp_on(void)
{
int i;
int ret = 1;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
if (mem_is_flash(cfi_flash_bank_addr(i))) {
/*
* We found at least one flash.
* We need to return 0 and call flash_init().
*/
ret = 0;
}
#if CONFIG_SYS_MAX_FLASH_BANKS > 1
else {
/*
* We might have a SRAM here.
* To prevent SRAM data from being destroyed,
* we set dummy address (SDRAM).
*/
flash_banks_list[i] = 0x80000000 + 0x10000 * i;
}
#endif
}
return ret;
}
#endif

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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/arm-mpcore.h>
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
static void *get_global_timer_base(void)
{
void *val;
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
return val + GLOBAL_TIMER_OFFSET;
}
unsigned long timer_read_counter(void)
{
/*
* ARM 64bit Global Timer is too much for our purpose.
* We use only lower 32 bit of the timer counter.
*/
return readl(get_global_timer_base() + GTIMER_CNT_L);
}
int timer_init(void)
{
/* enable timer */
writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
return 0;
}

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/*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_ARM_MPCORE_H
#define ARCH_ARM_MPCORE_H
/* Snoop Control Unit */
#define SCU_OFFSET 0x00
/* SCU Control Register */
#define SCU_CTRL 0x00
/* SCU Configuration Register */
#define SCU_CONF 0x04
/* SCU CPU Power Status Register */
#define SCU_PWR_STATUS 0x08
/* SCU Invalidate All Registers in Secure State */
#define SCU_INV_ALL 0x0C
/* SCU Filtering Start Address Register */
#define SCU_FILTER_START 0x40
/* SCU Filtering End Address Register */
#define SCU_FILTER_END 0x44
/* SCU Access Control Register */
#define SCU_SAC 0x50
/* SCU Non-secure Access Control Register */
#define SCU_SNSAC 0x54
/* Global Timer */
#define GLOBAL_TIMER_OFFSET 0x200
/* Global Timer Counter Registers */
#define GTIMER_CNT_L 0x00
#define GTIMER_CNT_H 0x04
/* Global Timer Control Register */
#define GTIMER_CTRL 0x08
/* Global Timer Interrupt Status Register */
#define GTIMER_STAT 0x0C
/* Comparator Value Registers */
#define GTIMER_CMP_L 0x10
#define GTIMER_CMP_H 0x14
/* Auto-increment Register */
#define GTIMER_INC 0x18
#endif /* ARCH_ARM_MPCORE_H */

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arch/arm/include/asm/arch-uniphier/bcu-regs.h Normal file
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/*
* UniPhier BCU (Bus Control Unit) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BCU_REGS_H
#define ARCH_BCU_REGS_H
#define BCU_BASE 0x50080000
#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4)
#define BCSCR0 (BCSCR(0))
#define BCSCR1 (BCSCR(1))
#define BCSCR2 (BCSCR(2))
#define BCSCR3 (BCSCR(3))
#define BCSCR4 (BCSCR(4))
#define BCSCR5 (BCSCR(5))
#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4)
#define BCIPPCCHR0 (BCIPPCCHR(0))
#define BCIPPCCHR1 (BCIPPCCHR(1))
#define BCIPPCCHR2 (BCIPPCCHR(2))
#define BCIPPCCHR3 (BCIPPCCHR(3))
#define BCIPPCCHR4 (BCIPPCCHR(4))
#define BCIPPCCHR5 (BCIPPCCHR(5))
#endif /* ARCH_BCU_REGS_H */

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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_BOARD_H
#define ARCH_BOARD_H
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
void support_card_reset(void);
void support_card_init(void);
int check_support_card(void);
#else
#define support_card_reset() do {} while (0)
#define support_card_init() do {} while (0)
static inline int check_support_card(void)
{
return 0;
}
#endif
static inline void uniphier_board_reset(void)
{
support_card_reset();
}
static inline void uniphier_board_init(void)
{
support_card_init();
}
#endif /* ARCH_BOARD_H */

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arch/arm/include/asm/arch-uniphier/boot-device.h Normal file
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/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
u32 get_boot_mode_sel(void);
struct boot_device_info {
u32 type;
char *info;
};
extern struct boot_device_info boot_device_table[];
#endif /* _ASM_BOOT_DEVICE_H_ */

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/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_LED_H
#define ARCH_LED_H
#include <config.h>
#define LED_CHAR_0 0x7e
#define LED_CHAR_1 0x0c
#define LED_CHAR_2 0xb6
#define LED_CHAR_3 0x9e
#define LED_CHAR_4 0xcc
#define LED_CHAR_5 0xda
#define LED_CHAR_6 0xfa
#define LED_CHAR_7 0x4e
#define LED_CHAR_8 0xfe
#define LED_CHAR_9 0xde
#define LED_CHAR_A 0xee
#define LED_CHAR_B 0xf8
#define LED_CHAR_C 0x72
#define LED_CHAR_D 0xbc
#define LED_CHAR_E 0xf2
#define LED_CHAR_F 0xe2
#define LED_CHAR_G 0x7a
#define LED_CHAR_H 0xe8
#define LED_CHAR_I 0x08
#define LED_CHAR_J 0x3c
#define LED_CHAR_K 0xea
#define LED_CHAR_L 0x70
#define LED_CHAR_M 0x6e
#define LED_CHAR_N 0xa8
#define LED_CHAR_O 0xb8
#define LED_CHAR_P 0xe6
#define LED_CHAR_Q 0xce
#define LED_CHAR_R 0xa0
#define LED_CHAR_S 0xc8
#define LED_CHAR_T 0x8c
#define LED_CHAR_U 0x7c
#define LED_CHAR_V 0x54
#define LED_CHAR_W 0xfc
#define LED_CHAR_X 0xec
#define LED_CHAR_Y 0xdc
#define LED_CHAR_Z 0xa4
#define LED_CHAR_SPACE 0x00
#define LED_CHAR_DOT 0x01
#define LED_CHAR_ (LED_CHAR_SPACE)
/** Macro to translate 4 characters into integer to display led */
#define LED_C2I(C0, C1, C2, C3) \
(~( \
(LED_CHAR_##C0 << 24) | \
(LED_CHAR_##C1 << 16) | \
(LED_CHAR_##C2 << 8) | \
(LED_CHAR_##C3) \
))
#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
#ifdef __ASSEMBLY__
#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
.macro raw_led_write data
ldr r0, =\data
ldr r1, =LED_ADDR
str r0, [r1]
.endm
#else /* __ASSEMBLY__ */
#include <asm/io.h>
#define led_write(C0, C1, C2, C3) \
do { \
raw_led_write(LED_C2I(C0, C1, C2, C3)); \
} while (0)
static inline void raw_led_write(u32 data)
{
writel(data, LED_ADDR);
}
#endif /* __ASSEMBLY__ */
#else /* CONFIG_SUPPORT_CARD_LED_BASE */
#define led_write(C0, C1, C2, C3)
#define raw_led_write(x)
#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
#endif /* ARCH_LED_H */

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/*
* UniPhier SBC (System Bus Controller) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SBC_REGS_H
#define ARCH_SBC_REGS_H
#define SBBASE_BASE 0x58c00100
#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
#define SBBASE0 (SBBASE(0))
#define SBBASE1 (SBBASE(1))
#define SBBASE2 (SBBASE(2))
#define SBBASE3 (SBBASE(3))
#define SBBASE4 (SBBASE(4))
#define SBBASE5 (SBBASE(5))
#define SBBASE6 (SBBASE(6))
#define SBBASE7 (SBBASE(7))
#define SBBASE_BANK_ENABLE (0x00000001)
#define SBCTRL_BASE 0x58c00200
#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
#define SBCTRL00 SBCTRL(0, 0)
#define SBCTRL01 SBCTRL(0, 1)
#define SBCTRL02 SBCTRL(0, 2)
#define SBCTRL03 SBCTRL(0, 3)
#define SBCTRL04 (SBCTRL_BASE + 0x100)
#define SBCTRL10 SBCTRL(1, 0)
#define SBCTRL11 SBCTRL(1, 1)
#define SBCTRL12 SBCTRL(1, 2)
#define SBCTRL13 SBCTRL(1, 3)
#define SBCTRL14 (SBCTRL_BASE + 0x110)
#define SBCTRL20 SBCTRL(2, 0)
#define SBCTRL21 SBCTRL(2, 1)
#define SBCTRL22 SBCTRL(2, 2)
#define SBCTRL23 SBCTRL(2, 3)
#define SBCTRL24 (SBCTRL_BASE + 0x120)
#define SBCTRL30 SBCTRL(3, 0)
#define SBCTRL31 SBCTRL(3, 1)
#define SBCTRL32 SBCTRL(3, 2)
#define SBCTRL33 SBCTRL(3, 3)
#define SBCTRL34 (SBCTRL_BASE + 0x130)
#define SBCTRL40 SBCTRL(4, 0)
#define SBCTRL41 SBCTRL(4, 1)
#define SBCTRL42 SBCTRL(4, 2)
#define SBCTRL43 SBCTRL(4, 3)
#define SBCTRL44 (SBCTRL_BASE + 0x140)
#define SBCTRL50 SBCTRL(5, 0)
#define SBCTRL51 SBCTRL(5, 1)
#define SBCTRL52 SBCTRL(5, 2)
#define SBCTRL53 SBCTRL(5, 3)
#define SBCTRL54 (SBCTRL_BASE + 0x150)
#define SBCTRL60 SBCTRL(6, 0)
#define SBCTRL61 SBCTRL(6, 1)
#define SBCTRL62 SBCTRL(6, 2)
#define SBCTRL63 SBCTRL(6, 3)
#define SBCTRL64 (SBCTRL_BASE + 0x160)
#define SBCTRL70 SBCTRL(7, 0)
#define SBCTRL71 SBCTRL(7, 1)
#define SBCTRL72 SBCTRL(7, 2)
#define SBCTRL73 SBCTRL(7, 3)
#define SBCTRL74 (SBCTRL_BASE + 0x170)
/* slower but LED works */
#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
/* faster but LED does not work */
#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
/* NOR flash needs more wait counts than SRAM */
#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
#define ROM_BOOT_ROMRSV2 0x59801208
#ifndef __ASSEMBLY__
#include <asm/io.h>
static inline int boot_is_swapped(void)
{
return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
}
#endif
#endif /* ARCH_SBC_REGS_H */

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/*
* UniPhier SC (System Control) block registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
#define SC_BASE_ADDR 0x61840000
#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184)
#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0)
#define SC_MPLLOSCCTL_MPLLST (0x1 << 1)
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
#define SC_CLKCTRL_CLK_MIO (0x1 << 11)
#define SC_CLKCTRL_CLK_UMC (0x1 << 4)
#define SC_CLKCTRL_CLK_NAND (0x1 << 2)
#define SC_CLKCTRL_CLK_SBC (0x1 << 1)
#define SC_CLKCTRL_CLK_PERI (0x1 << 0)
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
#endif /* ARCH_SC_REGS_H */

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/*
* UniPhier SG (SoC Glue) block registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SG_REGS_H
#define ARCH_SG_REGS_H
/* Base Address */
#define SG_CTRL_BASE 0x5f800000
#define SG_DBG_BASE 0x5f900000
/* Revision */
#define SG_REVISION (SG_CTRL_BASE | 0x0000)
#define SG_REVISION_TYPE_SHIFT 16
#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
#define SG_REVISION_MODEL_SHIFT 8
#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
#define SG_REVISION_REV_SHIFT 0
#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
#if defined(CONFIG_MACH_PH1_PRO4)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
#endif
#if defined(CONFIG_MACH_PH1_PRO4)
#define SG_PINSELBITS 4
#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
#define SG_PINSELBITS 8
#endif
#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
((n) * (SG_PINSELBITS) % 32)))
#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
/* Only for PH1-Pro4 */
#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
/* Input Enable */
#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
/* Pin Monitor */
#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <asm/io.h>
static inline void sg_set_pinsel(int n, int value)
{
writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
| SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
}
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
int size_mb = (size >> 20) / num;
u32 ret;
switch (size_mb) {
case 64:
ret = SG_MEMCONF_CH0_SIZE_64MB;
break;
case 128:
ret = SG_MEMCONF_CH0_SIZE_128MB;
break;
case 256:
ret = SG_MEMCONF_CH0_SIZE_256MB;
break;
case 512:
ret = SG_MEMCONF_CH0_SIZE_512MB;
break;
case 1024:
ret = SG_MEMCONF_CH0_SIZE_1024MB;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH0_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH0_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
int size_mb = (size >> 20) / num;
u32 ret;
switch (size_mb) {
case 64:
ret = SG_MEMCONF_CH1_SIZE_64MB;
break;
case 128:
ret = SG_MEMCONF_CH1_SIZE_128MB;
break;
case 256:
ret = SG_MEMCONF_CH1_SIZE_256MB;
break;
case 512:
ret = SG_MEMCONF_CH1_SIZE_512MB;
break;
case 1024:
ret = SG_MEMCONF_CH1_SIZE_1024MB;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH1_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH1_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */

67
arch/arm/include/asm/arch-uniphier/ssc-regs.h Normal file
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@ -0,0 +1,67 @@
/*
* UniPhier System Cache (L2 Cache) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_SSC_REGS_H
#define ARCH_SSC_REGS_H
#define SSCC 0x500c0000
#define SSCC_BST (0x1 << 20)
#define SSCC_ACT (0x1 << 19)
#define SSCC_WTG (0x1 << 18)
#define SSCC_PRD (0x1 << 17)
#define SSCC_WBWA (0x1 << 16)
#define SSCC_EX (0x1 << 13)
#define SSCC_ON (0x1 << 0)
#define SSCLPDAWCR 0x500c0030
#define SSCOPE 0x506c0244
#define SSCOPE_CM_SYNC 0x00000008
#define SSCOQM 0x506c0248
#define SSCOQM_TID_MASK (0x3 << 21)
#define SSCOQM_TID_BY_WAY (0x2 << 21)
#define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
#define SSCOQM_S_MASK (0x3 << 17)
#define SSCOQM_S_WAY (0x2 << 17)
#define SSCOQM_S_ALL (0x1 << 17)
#define SSCOQM_S_ADDRESS (0x0 << 17)
#define SSCOQM_CE (0x1 << 15)
#define SSCOQM_CW (0x1 << 14)
#define SSCOQM_CM_MASK (0x7)
#define SSCOQM_CM_DIRT_TOUCH (0x7)
#define SSCOQM_CM_ZERO_TOUCH (0x6)
#define SSCOQM_CM_NORM_TOUCH (0x5)
#define SSCOQM_CM_PREF_FETCH (0x4)
#define SSCOQM_CM_SSC_FETCH (0x3)
#define SSCOQM_CM_WB_INV (0x2)
#define SSCOQM_CM_WB (0x1)
#define SSCOQM_CM_INV (0x0)
#define SSCOQAD 0x506c024c
#define SSCOQSZ 0x506c0250
#define SSCOQWN 0x506c0258
#define SSCOPPQSEF 0x506c025c
#define SSCOPPQSEF_FE (0x1 << 1)
#define SSCOPPQSEF_OE (0x1 << 0)
#define SSCOLPQS 0x506c0260
#define SSCOLPQS_EF (0x1 << 2)
#define SSCOLPQS_EST (0x1 << 1)
#define SSCOLPQS_QST (0x1 << 0)
#define SSCOQCE0 0x506c0270
#define SSC_LINE_SIZE 128
#define SSC_NUM_ENTRIES 256
#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
#endif /* ARCH_SSC_REGS_H */

119
arch/arm/include/asm/arch-uniphier/umc-regs.h Normal file
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@ -0,0 +1,119 @@
/*
* UniPhier UMC (Universal Memory Controller) registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_UMC_REGS_H
#define ARCH_UMC_REGS_H
#define UMC_BASE 0x5b800000
/* SSIF registers */
#define UMC_SSIF_BASE UMC_BASE
#define UMC_CPURST 0x00000700
#define UMC_IDSRST 0x0000070C
#define UMC_IXMRST 0x00000714
#define UMC_HDMRST 0x00000718
#define UMC_MDMRST 0x0000071C
#define UMC_HDDRST 0x00000720
#define UMC_MDDRST 0x00000724
#define UMC_SIORST 0x00000728
#define UMC_GIORST 0x0000072C
#define UMC_HD2RST 0x00000734
#define UMC_VIORST 0x0000073C
#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
#define UMC_DVCRST 0x00000748 /* Pro4 */
#define UMC_RGLRST 0x00000750
#define UMC_VPERST 0x00000758
#define UMC_AIORST 0x00000764
#define UMC_DMDRST 0x00000770
#define UMC_HDMCHSEL 0x00000898
#define UMC_MDMCHSEL 0x0000089C
#define UMC_DVCCHSEL 0x000008C8
#define UMC_DMDCHSEL 0x000008F0
#define UMC_CLKEN_SSIF_FETCH 0x0000C060
#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
#define UMC_CLKEN_SSIF_WC 0x0000C07C
#define UMC_CLKEN_SSIF_RC 0x0000C080
#define UMC_CLKEN_SSIF_DST 0x0000C084
/* CA registers */
#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch))
/* DRAM controller registers */
#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch))
#define UMC_CMDCTLA 0x00000000
#define UMC_CMDCTLB 0x00000004
#define UMC_INITCTLA 0x00000008
#define UMC_INITCTLB 0x0000000C
#define UMC_INITCTLC 0x00000010
#define UMC_INITSET 0x00000014
#define UMC_INITSTAT 0x00000018
#define UMC_DRMMR0 0x0000001C
#define UMC_DRMMR1 0x00000020
#define UMC_DRMMR2 0x00000024
#define UMC_DRMMR3 0x00000028
#define UMC_SPCCTLA 0x00000030
#define UMC_SPCCTLB 0x00000034
#define UMC_SPCSETA 0x00000038
#define UMC_SPCSETB 0x0000003C
#define UMC_SPCSETC 0x00000040
#define UMC_SPCSETD 0x00000044
#define UMC_SPCSTATA 0x00000050
#define UMC_SPCSTATB 0x00000054
#define UMC_SPCSTATC 0x00000058
#define UMC_ACSSETA 0x00000060
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
#define UMC_RDATACTL_D1 0x00000608
#define UMC_WDATACTL_D1 0x0000060C
#define UMC_DATASET 0x00000610
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
#define UMC_DIOCTLA 0x00000C00
#define UMC_DFICUPDCTLA 0x00000C20
#ifndef __ASSEMBLY__
#include <linux/types.h>
static inline void umc_polling(u32 address, u32 expval, u32 mask)
{
u32 nmask = ~mask;
u32 data;
do {
data = readl(address) & nmask;
} while (data != expval);
}
static inline void umc_dram_init_start(void __iomem *dramcont)
{
writel(0x00000002, dramcont + UMC_INITSET);
}
static inline void umc_dram_init_poll(void __iomem *dramcont)
{
while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
;
}
#endif
#endif

49
arch/arm/include/asm/arch-vf610/imx-regs.h
View File

@ -103,9 +103,11 @@
/* DDRMC */
#define DDRMC_PHY_DQ_TIMING 0x00002613
#define DDRMC_PHY_DQS_TIMING 0x00002615
#define DDRMC_PHY_CTRL 0x01210080
#define DDRMC_PHY_CTRL 0x00210000
#define DDRMC_PHY_MASTER_CTRL 0x0001012a
#define DDRMC_PHY_SLAVE_CTRL 0x00012020
#define DDRMC_PHY_SLAVE_CTRL 0x00002000
#define DDRMC_PHY_OFF 0x00000000
#define DDRMC_PHY_PROC_PAD_ODT 0x00010101
#define DDRMC_PHY50_DDR3_MODE (1 << 12)
#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
@ -138,7 +140,7 @@
#define DDRMC_CR21_CCMAP_EN 1
#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
#define DDRMC_CR23_TDLL(v) ((v) & 0xff)
#define DDRMC_CR23_TDLL(v) ((v) & 0xffff)
#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
#define DDRMC_CR25_TREF_EN (1 << 16)
#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
@ -151,7 +153,7 @@
#define DDRMC_CR33_EN_QK_SREF (1 << 16)
#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
#define DDRMC_CR38_FREQ_CHG_EN (1 << 8)
#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8)
#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
@ -163,7 +165,7 @@
#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
#define DDRMC_CR70_REF_PER_ZQ(v) (v)
#define DDRMC_CR72_ZQCS_ROTATE (1 << 24)
#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24)
#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
@ -182,9 +184,10 @@
#define DDRMC_CR77_CS_MAP (1 << 24)
#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
#define DDRMC_CR77_SWAP_EN 1
#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF (1 << 24)
#define DDRMC_CR82_INT_MASK 0x1fffffff
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
@ -192,9 +195,17 @@
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
#define DDRMC_CR97_WRLVL_EN (1 << 24)
#define DDRMC_CR98_WRLVL_DL_0 (0)
#define DDRMC_CR99_WRLVL_DL_1 (0)
#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16)
#define DDRMC_CR102_RDLVL_REG_EN (1 << 8)
#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff)
#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16)
#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff)
#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
@ -208,20 +219,42 @@
#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16)
#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16)
#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16)
#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8)
#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff)
#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16)
#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff)
#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24)
#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16)
#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8)
#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff)
#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff)
#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v)
#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff)
#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff)
#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8)
#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf)
#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18)
#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14)
#define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3)
#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7)
#define DDRMC_CR158_TWR(v) ((v) & 0x3f)
#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16)
#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8)
#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

44
arch/arm/include/asm/arch-vf610/iomux-vf610.h
View File

@ -17,6 +17,8 @@
#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_OBE_IBE_ENABLE)
#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \
PAD_CTL_INPUT_DIFFERENTIAL)
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
@ -102,6 +104,7 @@ enum {
VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
@ -117,6 +120,7 @@ enum {
VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
@ -124,26 +128,26 @@ enum {
VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),

2
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@ -120,6 +120,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_MUX_MODE_SHIFT 20
#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
#define PAD_CTL_SPEED_MED (1 << 12)
#define PAD_CTL_SPEED_HIGH (3 << 12)

94
board/freescale/vf610twr/vf610twr.c
View File

@ -45,6 +45,7 @@ void setup_iomux_ddr(void)
VF610_PAD_DDR_A3__DDR_A_3,
VF610_PAD_DDR_A2__DDR_A_2,
VF610_PAD_DDR_A1__DDR_A_1,
VF610_PAD_DDR_A0__DDR_A_0,
VF610_PAD_DDR_BA2__DDR_BA_2,
VF610_PAD_DDR_BA1__DDR_BA_1,
VF610_PAD_DDR_BA0__DDR_BA_0,
@ -76,6 +77,7 @@ void setup_iomux_ddr(void)
VF610_PAD_DDR_WE__DDR_WE_B,
VF610_PAD_DDR_ODT1__DDR_ODT_0,
VF610_PAD_DDR_ODT0__DDR_ODT_1,
VF610_PAD_DDR_RESETB,
};
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
@ -88,30 +90,30 @@ void ddr_phy_init(void)
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
/* LPDDR2 only parameter */
writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
&ddrmr->phy[50]);
/* Processor Pad ODT settings */
writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
}
void ddr_ctrl_init(void)
@ -120,12 +122,12 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]);
writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
&ddrmr->cr[13]);
writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
@ -134,24 +136,23 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]);
writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]);
writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
@ -164,37 +165,45 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
&ddrmr->cr[74]);
writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
DDRMC_CR75_PLEN, &ddrmr->cr[75]);
writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
&ddrmr->cr[78]);
writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
&ddrmr->cr[87]);
writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
&ddrmr->cr[102]);
writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0),
&ddrmr->cr[117]);
writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
&ddrmr->cr[118]);
@ -205,23 +214,40 @@ void ddr_ctrl_init(void)
&ddrmr->cr[121]);
writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
&ddrmr->cr[123]);
writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
&ddrmr->cr[132]);
writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
&ddrmr->cr[138]);
writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
&ddrmr->cr[139]);
writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
&ddrmr->cr[143]);
writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),
&ddrmr->cr[144]);
writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
DDRMC_CR154_PAD_ZQ_MODE(1) |
DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2),
&ddrmr->cr[155]);
writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
ddr_phy_init();

8
configs/ph1_ld4_defconfig Normal file
View File

@ -0,0 +1,8 @@
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_LD4=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
S:CONFIG_SPL_NAND_DENALI=y

8
configs/ph1_pro4_defconfig Normal file
View File

@ -0,0 +1,8 @@
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_PRO4=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
S:CONFIG_SPL_NAND_DENALI=y

8
configs/ph1_sld8_defconfig Normal file
View File

@ -0,0 +1,8 @@
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_UNIPHIER=y
+S:CONFIG_MACH_PH1_SLD8=y
CONFIG_NAND_DENALI=y
CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
S:CONFIG_SPL_NAND_DENALI=y

6
doc/README.nand
View File

@ -215,12 +215,6 @@ Configuration Options:
Platform specific options
=========================
CONFIG_NAND_DENALI
Enables the denali.c driver.
CONFIG_SYS_NAND_DENALI_64BIT
Indicates that the Denali NAND controller is the 64-bit variant.
CONFIG_NAND_OMAP_GPMC
Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
GPMC controller is used for parallel NAND flash devices, and can

1
doc/git-mailrc
View File

@ -63,6 +63,7 @@ alias sunxi uboot, ijc, jwrdegoede
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
alias ti uboot, trini
alias uniphier uboot, masahiro
alias zynq uboot, monstr
alias avr32 uboot, abiessmann

1
drivers/mtd/Kconfig
View File

@ -0,0 +1 @@
source "drivers/mtd/nand/Kconfig"

42
drivers/mtd/nand/Kconfig Normal file
View File

@ -0,0 +1,42 @@
menu "NAND Device Support"
if !SPL_BUILD
config NAND_DENALI
bool "Support Denali NAND controller"
help
Enable support for the Denali NAND controller.
config SYS_NAND_DENALI_64BIT
bool "Use 64-bit variant of Denali NAND controller"
depends on NAND_DENALI
help
The Denali NAND controller IP has some variations in terms of
the bus interface. The DMA setup sequence is completely differenct
between 32bit / 64bit AXI bus variants.
If your Denali NAND controller is the 64-bit variant, say Y.
Otherwise (32 bit), say N.
config NAND_DENALI_SPARE_AREA_SKIP_BYTES
int "Number of bytes skipped in OOB area"
depends on NAND_DENALI
range 0 63
help
This option specifies the number of bytes to skip from the beginning
of OOB area before last ECC sector data starts. This is potentially
used to preserve the bad block marker in the OOB area.
endif
if SPL_BUILD
config SPL_NAND_DENALI
bool "Support Denali NAND controller for SPL"
help
This is a small implementation of the Denali NAND controller
for use on SPL.
endif
endmenu

1
drivers/mtd/nand/Makefile
View File

@ -12,6 +12,7 @@ NORMAL_DRIVERS=y
endif
obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o

231
drivers/mtd/nand/denali_spl.c Normal file
View File

@ -0,0 +1,231 @@
/*
* Copyright (C) 2014 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <linux/mtd/nand.h>
#include "denali.h"
#define SPARE_ACCESS 0x41
#define MAIN_ACCESS 0x42
#define PIPELINE_ACCESS 0x2000
#define BANK(x) ((x) << 24)
static void __iomem *denali_flash_mem =
(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
static void __iomem *denali_flash_reg =
(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
static const int flash_bank;
static uint8_t page_buffer[NAND_MAX_PAGESIZE];
static int page_size, oob_size, pages_per_block;
static void index_addr(uint32_t address, uint32_t data)
{
writel(address, denali_flash_mem + INDEX_CTRL_REG);
writel(data, denali_flash_mem + INDEX_DATA_REG);
}
static int wait_for_irq(uint32_t irq_mask)
{
unsigned long timeout = 1000000;
uint32_t intr_status;
do {
intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
debug("Uncorrected ECC detected\n");
return -EIO;
}
if (intr_status & irq_mask)
break;
udelay(1);
timeout--;
} while (timeout);
if (!timeout) {
debug("Timeout with interrupt status %08x\n", intr_status);
return -EIO;
}
return 0;
}
static void read_data_from_flash_mem(uint8_t *buf, int len)
{
int i;
uint32_t *buf32;
/* transfer the data from the flash */
buf32 = (uint32_t *)buf;
/*
* Let's take care of unaligned access although it rarely happens.
* Avoid put_unaligned() for the normal use cases since it leads to
* a bit performance regression.
*/
if ((unsigned long)buf32 % 4) {
for (i = 0; i < len / 4; i++)
put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
buf32++);
} else {
for (i = 0; i < len / 4; i++)
*buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
}
if (len % 4) {
u32 tmp;
tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
buf = (uint8_t *)buf32;
for (i = 0; i < len % 4; i++) {
*buf++ = tmp;
tmp >>= 8;
}
}
}
int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
{
uint32_t addr, cmd;
static uint32_t page_count = 1;
writel(ecc_en, denali_flash_reg + ECC_ENABLE);
/* clear all bits of intr_status. */
writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
addr = BANK(flash_bank) | page;
/* setup the acccess type */
cmd = MODE_10 | addr;
index_addr(cmd, access_type);
/* setup the pipeline command */
index_addr(cmd, PIPELINE_ACCESS | page_count);
cmd = MODE_01 | addr;
writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
return wait_for_irq(INTR_STATUS__LOAD_COMP);
}
static int nand_read_oob(void *buf, int page)
{
int ret;
ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
if (ret < 0)
return ret;
read_data_from_flash_mem(buf, oob_size);
return 0;
}
static int nand_read_page(void *buf, int page)
{
int ret;
ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
if (ret < 0)
return ret;
read_data_from_flash_mem(buf, page_size);
return 0;
}
static int nand_block_isbad(int block)
{
int ret;
ret = nand_read_oob(page_buffer, block * pages_per_block);
if (ret < 0)
return ret;
return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff;
}
/* nand_init() - initialize data to make nand usable by SPL */
void nand_init(void)
{
/* access to main area */
writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
/*
* These registers are expected to be already set by the hardware
* or earlier boot code. So we read these values out.
*/
page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
}
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
int block, page, column, readlen;
int ret;
int force_bad_block_check = 1;
page = offs / page_size;
column = offs % page_size;
block = page / pages_per_block;
page = page % pages_per_block;
while (size) {
if (force_bad_block_check || page == 0) {
ret = nand_block_isbad(block);
if (ret < 0)
return ret;
if (ret) {
block++;
continue;
}
}
force_bad_block_check = 0;
if (unlikely(column || size < page_size)) {
/* Partial page read */
ret = nand_read_page(page_buffer,
block * pages_per_block + page);
if (ret < 0)
return ret;
readlen = min(page_size - column, size);
memcpy(dst, page_buffer, readlen);
column = 0;
} else {
ret = nand_read_page(dst,
block * pages_per_block + page);
if (ret < 0)
return ret;
readlen = page_size;
}
size -= readlen;
dst += readlen;
page++;
if (page == pages_per_block) {
block++;
page = 0;
}
}
return 0;
}
void nand_deselect(void) {}

1
drivers/serial/Makefile
View File

@ -39,6 +39,7 @@ obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o

2
drivers/serial/serial.c
View File

@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize);
serial_initfunc(arm_dcc_initialize);
serial_initfunc(mxs_auart_initialize);
serial_initfunc(arc_serial_initialize);
serial_initfunc(uniphier_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
@ -250,6 +251,7 @@ void serial_initialize(void)
arm_dcc_initialize();
mxs_auart_initialize();
arc_serial_initialize();
uniphier_serial_initialize();
serial_assign(default_serial_console()->name);
}

204
drivers/serial/serial_uniphier.c Normal file
View File

@ -0,0 +1,204 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* Based on serial_ns16550.c
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <serial.h>
#define UART_REG(x) \
u8 x; \
u8 postpad_##x[3];
/*
* Note: Register map is slightly different from that of 16550.
*/
struct uniphier_serial {
UART_REG(rbr); /* 0x00 */
UART_REG(ier); /* 0x04 */
UART_REG(iir); /* 0x08 */
UART_REG(fcr); /* 0x0c */
u8 mcr; /* 0x10 */
u8 lcr;
u16 __postpad;
UART_REG(lsr); /* 0x14 */
UART_REG(msr); /* 0x18 */
u32 __none1;
u32 __none2;
u16 dlr;
u16 __postpad2;
};
#define thr rbr
/*
* These are the definitions for the Line Control Register
*/
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_DR 0x01 /* Data ready */
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
DECLARE_GLOBAL_DATA_PTR;
static void uniphier_serial_init(struct uniphier_serial *port)
{
const unsigned int mode_x_div = 16;
unsigned int divisor;
writeb(UART_LCR_WLS_8, &port->lcr);
divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK,
mode_x_div * gd->baudrate);
writew(divisor, &port->dlr);
}
static void uniphier_serial_setbrg(struct uniphier_serial *port)
{
uniphier_serial_init(port);
}
static int uniphier_serial_tstc(struct uniphier_serial *port)
{
return (readb(&port->lsr) & UART_LSR_DR) != 0;
}
static int uniphier_serial_getc(struct uniphier_serial *port)
{
while (!uniphier_serial_tstc(port))
;
return readb(&port->rbr);
}
static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
{
if (c == '\n')
uniphier_serial_putc(port, '\r');
while (!(readb(&port->lsr) & UART_LSR_THRE))
;
writeb(c, &port->thr);
}
static struct uniphier_serial *serial_ports[4] = {
#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
#else
NULL,
#endif
#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
#else
NULL,
#endif
#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
#else
NULL,
#endif
#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
#else
NULL,
#endif
};
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
static int eserial##port##_init(void) \
{ \
uniphier_serial_init(serial_ports[port]); \
return 0 ; \
} \
static void eserial##port##_setbrg(void) \
{ \
uniphier_serial_setbrg(serial_ports[port]); \
} \
static int eserial##port##_getc(void) \
{ \
return uniphier_serial_getc(serial_ports[port]); \
} \
static int eserial##port##_tstc(void) \
{ \
return uniphier_serial_tstc(serial_ports[port]); \
} \
static void eserial##port##_putc(const char c) \
{ \
uniphier_serial_putc(serial_ports[port], c); \
}
/* Serial device descriptor */
#define INIT_ESERIAL_STRUCTURE(port, __name) { \
.name = __name, \
.start = eserial##port##_init, \
.stop = NULL, \
.setbrg = eserial##port##_setbrg, \
.getc = eserial##port##_getc, \
.tstc = eserial##port##_tstc, \
.putc = eserial##port##_putc, \
.puts = default_serial_puts, \
}
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
DECLARE_ESERIAL_FUNCTIONS(0);
struct serial_device uniphier_serial0_device =
INIT_ESERIAL_STRUCTURE(0, "ttyS0");
#endif
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device uniphier_serial1_device =
INIT_ESERIAL_STRUCTURE(1, "ttyS1");
#endif
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device uniphier_serial2_device =
INIT_ESERIAL_STRUCTURE(2, "ttyS2");
#endif
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device uniphier_serial3_device =
INIT_ESERIAL_STRUCTURE(3, "ttyS3");
#endif
__weak struct serial_device *default_serial_console(void)
{
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
return &uniphier_serial0_device;
#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
return &uniphier_serial1_device;
#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
return &uniphier_serial2_device;
#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
return &uniphier_serial3_device;
#else
#error "No uniphier serial ports configured."
#endif
}
void uniphier_serial_initialize(void)
{
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
serial_register(&uniphier_serial0_device);
#endif
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
serial_register(&uniphier_serial1_device);
#endif
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
serial_register(&uniphier_serial2_device);
#endif
#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
serial_register(&uniphier_serial3_device);
#endif
}

4
include/configs/lsxl.h
View File

@ -8,6 +8,8 @@
#ifndef _CONFIG_LSXL_H
#define _CONFIG_LSXL_H
#define CONFIG_SYS_GENERIC_BOARD
/*
* Version number information
*/
@ -157,7 +159,7 @@
"standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
"setenv ncip; setenv gatewayip; setenv ethact; " \
"setenv bootfile; setenv dnsip; " \
"setenv bootsource hdd; run ser\0" \
"setenv bootsource legacy; run ser\0" \
"restore_env=run standard_env; saveenv; reset\0" \
"ser=setenv stdin serial; setenv stdout serial; " \
"setenv stderr serial\0" \

59
include/configs/ph1_ld4.h Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PH1_XXX_H
#define __PH1_XXX_H
/*
* Support Card Select
*
* CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
* CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
* CPLD is re-programmed for ARIMA board compatibility.
* No define - No support card.
*/
#if 0
#define CONFIG_PFC_MICRO_SUPPORT_CARD
#else
#define CONFIG_DCC_MICRO_SUPPORT_CARD
#endif
/*
* Serial Configuration
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
#if 1
#define CONFIG_UNIPHIER_SERIAL
#else
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SYS_UNIPHIER_UART_CLK 36864000
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_FREQ 1600
/*
* Memory Size & Mapping
*/
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#define CONFIG_SPL_TEXT_BASE 0x40000
#include "uniphier-common.h"
#endif /* __PH1_XXX_H */

61
include/configs/ph1_pro4.h Normal file
View File

@ -0,0 +1,61 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PH1_XXX_H
#define __PH1_XXX_H
/*
* Support Card Select
*
* CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
* CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
* CPLD is re-programmed for ARIMA board compatibility.
* No define - No support card.
*/
#if 0
#define CONFIG_PFC_MICRO_SUPPORT_CARD
#else
#define CONFIG_DCC_MICRO_SUPPORT_CARD
#endif
/*
* Serial Configuration
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
#if 1
#define CONFIG_UNIPHIER_SERIAL
#else
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SYS_UNIPHIER_UART_CLK 73728000
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
#define CONFIG_DDR_FREQ 1600
#define CONFIG_UNIPHIER_SMP
/*
* Memory Size & Mapping
*/
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xa0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#define CONFIG_SPL_TEXT_BASE 0x100000
#include "uniphier-common.h"
#endif /* __PH1_XXX_H */

61
include/configs/ph1_sld8.h Normal file
View File

@ -0,0 +1,61 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PH1_XXX_H
#define __PH1_XXX_H
/*
* Support Card Select
*
* CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
* CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
* CPLD is re-programmed for ARIMA board compatibility.
* No define - No support card.
*/
#if 0
#define CONFIG_PFC_MICRO_SUPPORT_CARD
#else
#define CONFIG_DCC_MICRO_SUPPORT_CARD
#endif
/*
* Serial Configuration
* SoC UART : enable CONFIG_UNIPHIER_SERIAL
* On-board UART: enable CONFIG_SYS_NS16550_SERIAL
*/
#if 1
#define CONFIG_UNIPHIER_SERIAL
#else
#define CONFIG_SYS_NS16550_SERIAL
#endif
#define CONFIG_SYS_UNIPHIER_UART_CLK 80000000
#define CONFIG_SMC911X
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_FREQ 1333
/* #define CONFIG_DDR_STANDARD */
/*
* Memory Size & Mapping
*/
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#define CONFIG_SPL_TEXT_BASE 0x40000
#include "uniphier-common.h"
#endif /* __PH1_XXX_H */

46
include/configs/sheevaplug.h
View File

@ -1,5 +1,6 @@
/*
* (C) Copyright 2009
* (C) Copyright 2009-2014
* Gerald Kerma <dreagle@doukki.net>
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
@ -22,13 +23,27 @@
#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Compression configuration
*/
#define CONFIG_BZIP2
#define CONFIG_LZMA
#define CONFIG_LZO
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
@ -54,8 +69,8 @@
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
#define CONFIG_ENV_ADDR 0x80000
#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
/*
* Default environment variables
@ -64,8 +79,10 @@
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"${x_bootcmd_usb}; bootm 0x6400000;"
#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
#define CONFIG_MTDPARTS \
"mtdparts=orion_nand:512K(uboot)," \
"512K(env),1M(script),6M(kernel)," \
"12M(ramdisk),4M(spare),-(rootfs)"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
@ -73,6 +90,11 @@
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
#define MTDIDS_DEFAULT "nand0=orion_nand"
#define MTDPARTS_DEFAULT \
"mtdparts="CONFIG_MTDPARTS
/*
* Ethernet Driver configuration
*/
@ -91,10 +113,24 @@
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
#endif /* CONFIG_CMD_MMC */
/*
* SATA driver configuration
*/
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_DOS_PARTITION
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /* CONFIG_CMD_IDE */
/*
* File system
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI

266
include/configs/uniphier-common.h Normal file
View File

@ -0,0 +1,266 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* U-boot - Common settings for UniPhier Family */
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) && \
defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
are defined. Select only one of them."
#endif
/*
* Support card address map
*/
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
# define CONFIG_SUPPORT_CARD_BASE 0x08000000
# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
#endif
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK 12288000
#define CONFIG_SYS_NS16550_REG_SIZE -2
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800
#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900
#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00
#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00
/*-----------------------------------------------------------------------
* MMU and Cache Setting
*----------------------------------------------------------------------*/
/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
/* Comment out the following to enable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_TIMESTAMP
/* FLASH related */
#define CONFIG_MTD_DEVICE
/*
* uncomment the following to disable FLASH related code.
*/
/* #define CONFIG_SYS_NO_FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MONITOR_BASE 0
#define CONFIG_SYS_FLASH_BASE 0
/*
* flash_toggle does not work for out supoort card.
* We need to use flash_status_poll.
*/
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_FLASH_BANKS_LIST {0x00000000}
# define CONFIG_SYS_FLASH_BANKS_SIZES {0x02000000}
#endif
#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_FLASH_BANKS_LIST {0x04000000}
# define CONFIG_SYS_FLASH_BANKS_SIZES {0x04000000}
#endif
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_GENERIC_BOARD
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_CONS_INDEX 1
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
*/
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x0
/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
/*
* By default, ARP timeout is 5 sec.
* The first ARP request does not seem to work.
* So we need to retry ARP request anyway.
* We want to shrink the interval until the second ARP request.
*/
#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_TIME
#define CONFIG_CMD_NAND /* NAND flash suppport */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* Network Configuration
*/
#define CONFIG_ETHADDR 00:21:83:24:00:00
#define CONFIG_SERVERIP 192.168.11.1
#define CONFIG_IPADDR 192.168.11.10
#define CONFIG_GATEWAYIP 192.168.11.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 0x84000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_BOOTFILE "fit.itb"
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_BOOTCOMMAND "run $bootmode"
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs $bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
"tftpboot; bootm;"
#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"image_offset=0x00080000\0" \
"image_size=0x00f00000\0" \
"verify=n\0" \
"autostart=yes\0" \
"norboot=run add_default_bootargs;" \
"bootm $image_offset\0" \
"nandboot=run add_default_bootargs;" \
"nand read $loadaddr $image_offset $image_size;" \
"bootm\0" \
"add_default_bootargs=setenv bootargs $bootargs" \
" console=ttyS0,$baudrate\0" \
/* FIT support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
/* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_HAVE_ARM_SECURE
/* Memory Size & Mapping */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
/* Thre is no memory hole */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
#else
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
#endif
#define CONFIG_SYS_TEXT_BASE 0x84000000
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_BOARD_POSTCLK_INIT
#else
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */