Commit Graph

106 Commits

Author SHA1 Message Date
Stefan Roese
dfaf6a5797 CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined
Since commit 86cf1c8285 ("configs: Migrate CONFIG_NR_DRAM_BANKS") &
commit 999a772d9f ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"),
CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default).
It makes no sense to still carry code that is guarded with
"#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes
all these unreferenced code paths.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-26 09:19:16 +02:00
Suneel Garapati
f0c369284d pci: pci-uclass: Check validity of ofnode
Add check if the referenced ofnode is valid.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
a3fac3f395 pci: pci-uclass: Add support for Alternate-RoutingID capability
If ARI capability is found on device, use it to update next function
number in bus scan and also helps to skip unnecessary bdf scans.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
51eeae91c5 pci: pci-uclass: Add VF BAR map support for Enhanced Allocation
Makes dm_pci_map_bar API available to map BAR for Virtual function
PCI devices which support Enhanced Allocation.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
b8852dcfcb pci: pci-uclass: Add support for Single-Root I/O Virtualization
SR-IOV - Single Root I/O Virtualization
PF - Physical Function VF - Virtual Function

If SR-IOV capability is present, use it to initialize Virtual Function
PCI device instances. pci_sriov_init function will read SR-IOV
registers to create VF devices under the PF PCI device and also bind
driver if available. This function needs to be invoked from Physical
function device driver which expects VF device support, creating
minimal impact on existing framework.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
636cc1773a pci: pci-uclass: Add support for Enhanced Allocation in Bridges
If Enhanced Allocation capability is present in bridges, use it
to read the fixed sub-ordinate bus number.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
4cf56ec07f pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 08:01:16 +02:00
Suneel Garapati
bc30140d20 pci: pci-uclass: Make DT subnode parse optional
Parse subnode DT properties only if parent node is valid.
Otherwise, assert is triggered on ofnode_valid in ofnode_first_subnode
from dev_for_each_subnode.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Suneel Garapati
b3699a13a6 pci: pci-uclass: Fix incorrect argument in map_physmem
Fix argument ordering for map_physmem() called in dm_pci_map_ea_bar().
Additinally minor spelling correction.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
e002474158 pci: pci-uclass: Dynamically allocate the PCI regions
Instead of using a fixed length pre-allocated array of regions, this
patch moves to dynamically allocating the regions based on the number
of available regions plus the necessary regions for DRAM banks.

Since MAX_PCI_REGIONS is not needed any more, its removed completely
with this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2020-08-25 05:41:09 +02:00
Stefan Roese
3b7cd265b8 pci: pci-uclass: Remove #ifdef CONFIG_NR_DRAM_BANKS as its always set
Since the migration to Kconfig, CONFIG_NR_DRAM_BANKS is configured for
all boards. Hence we can remove the conditional compilation and the code
path that will never get compiled.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
2020-08-25 05:41:09 +02:00
Rayagonda Kokatanur
143eb5b1ca drivers: pci: add api to get dma regions
Add api to get dma regions.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2020-08-14 09:43:21 -04:00
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
f1f4438218 pci: Avoid auto-config when chain loading
When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:40:16 +08:00
Simon Glass
9ece4b090f pci: Adjust dm_pci_read_bar32() to return errors correctly
At present if reading a BAR returns 0xffffffff then the value is masked
and a different value is returned. This makes it harder to detect the
problem when debugging.

Update the function to avoid masking in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-04-16 14:36:28 +08:00
Simon Glass
d8c7fb5036 dm: pci: Allow disabling auto-config for a device
Add a means to avoid configuring a device when needed. Add an explanation
of why this is useful to the binding file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16 14:36:28 +08:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
194fca9130 dm: pci: Update a few more interfaces for const udevice *
Tidy up a few places where const * should be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
c4e72c4ad8 dm: pci: Update the PCI read_config() method to const dev *
At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
4886287ee4 pci: Print a warning if the bus is accessed before probing
It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
6dd4b01432 dm: pci: Move pci_get_devfn() into a common file
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.

To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.

Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Simon Glass
2206ac248a dm: pci: Allow delaying auto-config until after relocation
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.

This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Michael Walle
a6cd597a78 drivers: pci: ignore disabled devices
PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-05 10:28:38 -05:00
Simon Glass
90c668605f pci: Disable autoconfig in SPL
At present U-Boot runs autoconfig in SPL but this is best left to U-Boot
proper. For TPL and SPL we can normally used fixed BARs and save code size
and time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:42 +08:00
Simon Glass
0911569b28 pci: Show the result of binding a device
Update the debugging info a little to show the result of trying to bind
a PCI device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:42 +08:00
Simon Glass
07f2f58b94 x86: fsp: Create a common fsp_support.h header
Many support functions are common between FSP1 and FSP2. Add a new header
to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove forward declarations in fsp_support.h]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:53:41 +08:00
Simon Glass
8331188615 x86: Rename existing FSP code to fsp1
Since there is now a new version of the FSP and it is incompatible with
the existing version, move the code into an fsp1 directory. This will
allow us to put FSP v2 code into an fsp2 directory.

Add a Kconfig which defines which version is in use.

Some of the code in this new fsp1/ directory is generic across both FSPv1
and FSPv2. Future patches will address this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:50:08 +08:00
Marek Behún
60ee60944b pci: ensure enumeration of all devices in pci_init
Use the uclass_first_device_check and uclass_next_device_check functions
instead of uclass_first_device and uclass_next_device in pci_init. This
ensures that all PCI devices are tried to be probed. Currently if a
device fails to probe, the enumeration stops and the devices which come
after the failed device are not probed.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-12 21:07:58 -04:00
Alex Marginean
b8e1f8270c drivers: pci: add API to issue FLR on a PCI function if supported
Adds dm_pci_flr API that issues a Function Level reset on a PCI-e function,
if FLR is supported.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Alex Marginean
0b143d8ab2 drivers: pci: add map_bar support for Enhanced Allocation
Makes dm_pci_map_bar API available for integrated PCI devices that
support Enhanced Allocation instead of the original PCI BAR mechanism.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Thierry Reding
d94d9aa675 pci: Add boundary check for hose->regions
Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Tom Rini
bdac5e18a8 Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me
- Move Armada XP / 38x LCD driver to DM_VIDEO from me
- Add uDPU board (Armada-3720) from Vladimir

[trini: Fix warning in pci-uclass.c by removing ret from
	pci_uclass_child_post_bind as it no longer calls functions with
        a return code to catch.]
Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05 12:29:59 -05:00
Stefan Roese
b52142004f pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-05 14:22:24 +01:00
Hou Zhiqiang
2a87f7fdd5 dm/pci: Change the first CFG read to Vendor ID in enumeration
As the PCIe specification recommend reading the Vendor ID register
to determine if a Function is present, read the Vendor ID of a
non-existent Function must not result in system error, so we'd better
make the first CFG read to Vendor ID instead of Header Type register
in the PCIe enumeration.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-20 19:14:22 -07:00
Bin Meng
a8c5f8d3d0 dm: pci: Add APIs to find next capability and extended capability
This introduces two new APIs dm_pci_find_next_capability() and
dm_pci_find_next_ext_capability() to get PCI capability address
and PCI express extended capability address for a given PCI device
starting from a given offset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:28 -08:00
Marek Vasut
02e4d38d87 pci: Support parsing PCI controller DT subnodes
The PCI controller can have DT subnodes describing extra properties
of particular PCI devices, ie. a PHY attached to an EHCI controller
on a PCI bus. This patch parses those DT subnodes and assigns a node
to the PCI device instance, so that the driver can extract details
from that node and ie. configure the PHY using the PHY subsystem.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-20 15:23:38 -04:00
Masahiro Yamada
dee37fc99d Remove <inttypes.h> includes and PRI* usages in printf() entirely
In int-ll64.h, we always use the following typedefs:

  typedef unsigned int         u32;
  typedef unsigned long        uintptr_t;
  typedef unsigned long long   u64;

This does not need to match to the compiler's <inttypes.h>.
Do not include it.

The use of PRI* makes the code super-ugly.  You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:17 -04:00
Bin Meng
dac01fd89d dm: pci: Add APIs to find capability and extended capability
This introduces two new APIs dm_pci_find_capability() and
dm_pci_find_ext_capability() to get PCI capability address and
PCI express extended capability address for a given PCI device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
ed698aa7de dm: pci: Assign correct driver data when binding a driver
The correct driver data comes from the matching 'id' instead of
'find_id' in pci_find_and_bind_driver().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
64e45f73bd dm: pci: Fix scanning multi-function device
The flag to control whether to scan multi-function device during
enumeration should be cleared at the beginning of each iteration
if the device's function number equals to zero.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Bin Meng
1f6b08b969 dm: pci: Extract vendor/device id in child_post_bind()
Currently only devfn is extracted in child_post_bind(). Now that
we have the live-tree version API to look up PCI vendor and device
id from the compatible string, let's extract and save them too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-08 12:49:31 +01:00
Christian Gmeiner
6f95d89c71 dm: pci: Use a 1:1 mapping for bus <-> phy addresses
If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.

This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Christian Gmeiner
f2825f6ec0 dm: pci: Make ranges dt property optional
If we use U-Boot as coreboot payload with a generic dts without
any ranges specified we fail in pci pre_probe and our pci bus
is not usable.

So convert decode_regions(..) into a void function and do the simple
error handling there.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message and checkpatch warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Tuomas Tynkkynen
52ba907328 PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set
Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with
the 'highmem=off' parameter passed to QEMU's virt machine. The reason is
that when 'highmem' is not disabled, QEMU appends 64-bit a memory
resource to the PCI controller's regions property in DT in addition to
the 32-bit PCI memory window in low memory. And the current DT parsing
code picks the last (thus the 64-bit one) memory resource, whose address
eventually gets silently truncated to 32 bits because
CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break.

Avoid this problem by ignoring memory regions whose addresses are above
the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Bin Meng
ee1109bb45 dm: pci: Avoid setting a PCI region that has 0 size
It makes no sense to set a PCI region that has 0 size.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30 16:05:08 +08:00
Bin Meng
1eaf7800b6 dm: pci: Check board information pointer in decode_regions()
PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.

With this commit, Intel Galileo board boots again.

Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-30 16:05:08 +08:00