Add ahci compatible support for ls2080a soc.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
[YS: add fallthrough comment]
Reviewed-by: York Sun <york.sun@nxp.com>
Add ahci compatible support for ls1088a soc.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: remove line continuation in quoted string]
Reviewed-by: York Sun <york.sun@nxp.com>
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
IFC driver changes to implement the chipselect mappings at run time.
Defines init_early_memctl_regs and init_final_memctl_regs with
chipselect dynamic mapping for nor and nand boot.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
This reverts commit 6f57c34473 since it
does not seem to work at least on rk3399.
The Rockchip Technical Reference Manual (TRM) for the rk3399 says the baud
rate prescaler register is readable only when USR[0] is zero. Since this
bit is defined as "reserved" in the socfpga cylcone5 TRM, let's rather
drop this than making the ns16550 debug uart more platform specific.
Reported-by: Roosen Henri <Henri.Roosen@ginzinger.com>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com
This release is fully packed with lots of glorious improvements in UEFI
land again!
- Make PE images more standards compliant
- Improve sandbox support
- Improve correctness
- Fix RISC-V execution on virt model
- Honor board defined top of ram (fixes a few boards)
- Imply DM USB access when distro boot is available
- Code cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJcBYKAAAoJECszeR4D/txgBgwQALmYioI67R5/Iizpv7bg+rIQ
0TyPKZHmfHtVjGHd5X4X+9NBsoaSKqGnoI12bJ+V9hIMuiu5qFKyM3icTOOJ6LI6
wggnvMWZl5nfZmdEgETHTmaZkQZzKwhzbftGlGf2j19FdDk1OOI7hRNLeaIZUTv0
VHiUV68PP/1Of1y7iqB5jij1wTUHWlCufKjGXELP0bAXx86/tecgCuvjBihXizz/
sMsCxEF8++pb5l/l4yFEkKd5rr5D/ZkKMLR4KniZVq2qP1S4calolP14ykHN+a/l
uKP4e4GDuYyrgXXTNRFhVTlaAn18bmvxH4ialnpYVZKRtfsdHPHQXfqmgf8ZgJPE
JK3mmG6eLCbBPeND2Yz3b7G/Ec04z+RJXx0hriyLdejLgp5jM9SBtygiz6FmQLpQ
VfDJNEWV7ot6Ejou55O0d9u5ATF0jAd4tikmsrStWWZOVHvie6nG0wFYiRxnWCKP
sid0p7lWSUKEl0sAvA0LglNMzd4tCAq7vtkfLj/BVrDc9Jpir9CVJ13ppXIGk1HC
YIGWLo0uXAGC9wgRE7ZgGCKtQ6VFZRbSiJQOowi4MrHzHXH218oSNz2w25tAVTBw
le2WbxlGNYhV1xnoWMks1GTdWGQDCXdfBAhfzRIvQq2kz4z9V8hzpnVDIk2ZL3L1
o3nqUatR0ZVXPcinf+Ke
=6o9t
-----END PGP SIGNATURE-----
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-12-03
This release is fully packed with lots of glorious improvements in UEFI
land again!
- Make PE images more standards compliant
- Improve sandbox support
- Improve correctness
- Fix RISC-V execution on virt model
- Honor board defined top of ram (fixes a few boards)
- Imply DM USB access when distro boot is available
- Code cleanups
This patch adds a DM driver for the MPC8xx watchdog.
Basically, the watchdog is enabled by default from the start and
SYPCR register has to be writen once to set the timeout and/or
deactivate the watchdog. Once written, it cannot be written again.
It means that wdt_stop() can be called before wdt_start() to stop the
watchdog, but cannot be called if wdt_start() has been called.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
After this change the m41t62.c can be used with RTC subsystem (i.e. date
command) which uses device model (DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
This change facilitates the conversion of m41t62 RTC driver to device
model (DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
This patch moves the RTC M41T62 config define to Kconfig.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This patch modifies the meson clock driver to use syscon/regmap like
the Linux kernel does, as it is needed if we want to share the same
DTS files.
DTS files are synchronized from Linux 4.19.
Signed-off-by: Loic Devulder <ldevulder@suse.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Add support for the HS400 mode to SDHI driver. This uses the up-tune
mechanism from already supported HS200 tuning.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Move the tap_pos variable, which is the HS200/HS400/SDR104 calibration
offset, into private data, so it can be passed around. This is done in
preparation for the HS400 mode, which needs to adjust this value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Filter out HS400 support on SoCs where HS400 is not supported yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Reorder the tmio_sd_set_clk_rate() function such that it handles all
of the clock requiests correctly. Specifically, before this patch,
clock request with (mmc->clock == 0 && mmc->clk_disable) could leave
the clock enabled, as the function would exit on if (!mmc->clock)
condition on top and will not handle the mmc->clk_disable at all.
Rather than band-aid fixing just that particular problem, reorder
the entire function to make it easier to understand and verify that
all the cases are covered. The function has three sections now:
First, if mmc->clock != 0, we calculate divider for the SD block.
Second, if mmc->clock != 0 and SD block clock are enabled and
current divider is not equal to the new divider, then
stop the clock and update the divider.
Third, if mmc->clk_disable is set, disable the clock, otherwise
enable the clock. This happens independently of divider
update now.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The TMIO core has a feature where it can automatically disable clock output
when the bus is not in use. While this is useful, it also interferes with
switching the bus to 1.8V and other background tasks of the SD/MMC cards,
which require clock to be enabled.
This patch respects the mmc->clk_disable and only disables the clock when
the MMC core requests it. Otherwise the clock are continuously generated
on the bus.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.
Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
renesas and socionext platforms
Add HS400 properties parsing support to mmc_of_parse().
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
The SDHI clock must be configured differently for HS200/HS400/SDR104
modes. Add support for reconfiguring the SDHI clock settings into the
clock driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The USB storage driver does not compile when CONFIG_BLK is set,
but DM_USB is not set, as we're missing the DM device links for
CONFIG_BLK enabled code paths.
So far it looks like nobody fell into this trap, because no board
enabled CONFIG_BLK and CONFIG_USB_STORAGE while not enabling
CONFIG_DM_USB, but we should still reflect that dependency properly
in Kconfig so that implicit enabling of CONFIG_USB_STORAGE works.
Signed-off-by: Alexander Graf <agraf@suse.de>
When an operating system started via bootefi tries to reset or power off
this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system
the actual reset relies on PSCI. Depending on whether the PSCI firmware
resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC
or an SMC command has to be issued.
The current implementation always uses SMC. This results in crashes on
systems where the PSCI firmware is implemented in the hypervisor, e.g.
qemu-arm64_defconfig.
The logic to decide which call is needed based on the device tree is
already implemented in the PSCI firmware driver. During the EFI runtime
the device driver model is not available. But we can minimize code
duplication by merging the EFI runtime reset and poweroff code with
the PSCI firmware driver.
As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff
and reset_misc routines let's move them into the same code module.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Variable 'days' must be defined as signed int. Otherwise the conversion
fails for some dates, e.g. 2004-08-25. Cf function rtc_time64_to_tm() in
the Linux kernel source.
Fixes: 992c1db455 "drivers: rtc: resolve year 2038 problem in rtc_to_tm"
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason)
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlwBjx8ACgkQfxc6PpAI
rebWEAf+PMc/M3X6cCKm+8P9xTNFv0gv234HVke1eTDG3eyZB6WQnJn5CS0LwyPj
JUfwk4xK0Sqev/sQ6RuzmxmPAgla6UrEFB355tiZRBtFsMgf8bfevOqbxVqMbZl/
bOe4YsFJ3sAgQDuhi2C5xzm2speGtaB8Qy8s1Zlv2sx3zEnLgRqVgeEVHzulZsk3
gAlWKN3ys6EueYnOladjrrvrfOX8SQKYbThI+ACy7suZbtasGRITwP/4fQoXtmOl
39e9WsiW6DBRW1sxNxpixrOS5trgWjOOFiKlY3GNWP+N34+9vYASwuBWwRWqfgXo
cmelT6AcGiPUbHyr4k0CJHKCJlSbaQ==
=p83K
-----END PGP SIGNATURE-----
Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dm
Fix sound on sandbox
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason)
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.
The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c).
Tested on RK3399-Q7 on Haikou base board.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The "Flamingo" carrier-board for the RK3399-Q7 has a RV3029 populated
and the application will use the off-module RV3029 RTC including the
battery backed SRAM.
To support this use case, this commit includes the following changes:
* updates the rv3029 driver to use DM
* implements the read8/write8 operations
This syncs the implementation with the Linux code (based on 4.17),
porting the trickle-charger support from there (with improvements to
avoid unnecessary EEPROM updates) and adheres to the Linux DTS
binding.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The MicroCrystal RV3029 driver didn't have a Kconfig entry and was not used
anywhere. Add it to Kconfig to make it selectable.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There was an incorrect check when looping and finding the first
fast enough frequency in the freq_rang table. The code did
actually return the first that was either exactly correct or
too slow.
Signed-off-by: Richard Röjfors <richard@puffinpack.se>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There was a copy and paste error where the data
enable setting was written to the version register.
Signed-off-by: Richard Röjfors <richard@puffinpack.se>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Currently the else part of ofnode_get_addr_index function
does not fetch addresses based on the index but rather just
returns the base address. Fix that.
Signed-off-by: Keerthy <j-keerthy@ti.com>
At present these functions are not accessible outside the TPM library, but
in some cases we need to call them. Export them in the header file and add
a define for the SHA1 digest size.
Also adjust tpm_open() to call tpm_close() first so that the TPM is in a
known state before opening (e.g. by a previous phase of U-Boot).
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this value is hard-coded in the function that generates a
square wave. Since sample rates vary between different hardware, it makes
more sense to have this as a parameter.
Update the function and its users.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function currently outputs twice as much data as it should and
overwrites its buffer as a result. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some RTC chips have child drivers, e.g. to provide access to their
non-volatile RAM. Scan for these when binding.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sandbox i2c works using emulation drivers which are currently children of
the i2c device:
rtc_0: rtc@43 {
reg = <0x43>;
compatible = "sandbox-rtc";
emul {
compatible = "sandbox,i2c-rtc";
};
};
In this case the emulation device is attached to i2c bus on address 0x43
and provides the Real-Time-Clock (RTC) functionality.
However this is not ideal, since every device on an I2C bus has a child
device. This is only really the case for sandbox, but we want to avoid
special-case code for sandbox.
A better approach seems to be to add a separate node on the bus, an
'emulation parent'. This can be given a bogus address (such as 0xff) and
hides all the emulators away. Then we can use a phandle to point from the
device to the correct emualtor, and only on sandbox. The code to find an
emulator does not interfere with normal i2c operation.
Add a new UCLASS_I2C_EMUL_PARENT uclass which allows finding an emulator
given a bus, and finding a bus given an emulator. This will be used in a
follow-on patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
