The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.
The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".
An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed by: Peter Korsgaard <peter@korsgaard.com>
Add a defconfig and dts file for the Empire Electronix M712 tablet, this
is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on
the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV
wifi chip and a DMART06 (1238a4) accelerometer.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Sync dts files with the current (Aug 18th 2016) state of Maxime's
linux/sunxi/for-next repo.
Note this commit also updates configs/MSI_Primo81_defconfig,
adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary
because the tablet does not have a reachable uart so the dts sync
drops its serial0 alias.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a defconfig and dts file for tablets using the generic inet-q972 PCB.
Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host,
micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot,
(mini) power-barrel and an usb wifi module.
This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Ensure appropriate error messages are generated. Previously all errors
indicated that the serdes was already in use. Now appropriate error
messages are given.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The nvidia,bpmp property is left over from an old BPMP I2C binding, and
shouldn't be present. Remove it from the SoC DT file, and update the
I2C driver not to parse it; the value wasn't used for anything any more
anyway.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra SDHCI binding dictates that the reseet name for the Tegra SDHCI
clock be "sdhci" not "sdmmc", and that the clock is accessed by index
rather than by name. Fix the Tegra186 DT and MMC driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra I2C binding dictates that the clock name for the Tegra I2C clock
be "div-clk" not "i2c". Fix the Tegra186 DT and I2C driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no reason to duplicate code for DRA7xx platforms as there
can be Rail grouping. The maximum voltage detection algorithm can still
be run on other platforms with no Rail grouping and does not harm as
it gives the same result.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
gpio_en field is introduced to detect if pmic is controlled by GPIO.
Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms
and remove the #ifndefs.
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The bootz and booti commands rely on common functionality that is found
in common/bootm.c and common/bootm_os.c. They do not however rely on
the rest of cmd/bootm.c to be implemented so split them into their own
files. Have various Makefiles include the required infrastructure for
CONFIG_CMD_BOOT[IZ] as well as CONFIG_CMD_BOOTM. Move the declaration
of 'images' over to common/bootm.c.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
BLANCHE is development board based on R-Car V2H SoC (R8A7792)
This commit supports the following periherals:
- SCIF, Ethernet, QSPI, MMC
Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Salvator-x is an entry level development board based on
R-Car H3 SoC (R8A7795). This commit supports SCIF only.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Renesas R8A7795 is CPU with Cortex-a57.
This supports the basic register definition and GPIO and
framework of PFC.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The K2G EVM from TI has an SD card slot as
well as onboard eMMC for data storage.
Enable support for these.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
K2G SoC from TI has two MMC/SD controllers.
Add device tree data for these.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The firmware on TC2 needs to be configured appropriately before booting
in nonsec mode will work as expected, so test for this and fall back to
sec mode if required.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Bring in required device tree file and bindings from Linux.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The L4T kernel complains about a CSITE clock rate above 144MHz, presumably
because the HW is only characterized for a clock less than that. Adjust the
rate to 136MHz to avoid the warning and stay in spec.
Signed-off-by: Bryan Wu <pengw@nvidia.com>
(swarren, re-wrote commit description)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Currently, ft_system_setup() is implemented by board*.c, which are a bit
of a dumping ground for a bunch of unrelated functionality, and separate
versions exist for pre-Tegra186 and Tegra186. Move the implementation into
a separate file to separate functionality, and allow sharing.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
p2771-0000 has a couple of PCIe ports; one physically x4 desktop PCI
connector (which may run at x2 electrically, depending on the board
version and configuration) and a x1 connection to the M.2 slot (which may
not be active, depending on the board version and configuration). This
change enables those.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Now that clock and reset drivers exist for Tegra186, we can enable the SD
card controller. Now that a BPMP I2C driver exists for Tegra186, we can
communicate with the PMIC to enable power to the SD card. Hook up the DT
content and board code required to make the SD card work.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Linux stopped the use of keyword 'boolean' in Kconfig.
Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
