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https://github.com/brain-hackers/u-boot-brain
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ARM: at91/dt: Add device tree for SAMA5D2 Xplained
Add device tree for SAMA5D2 Xplained board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
This commit is contained in:
Wenyou Yang
Andreas Bießmann
parent
256a3f2466
commit
2c4b2dd289
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@ -270,6 +270,9 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
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k2e-evm.dtb \
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k2g-evm.dtb
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dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
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at91-sama5d2_xplained.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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200
arch/arm/dts/at91-sama5d2_xplained.dts
Normal file
200
arch/arm/dts/at91-sama5d2_xplained.dts
Normal file
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@ -0,0 +1,200 @@
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/dts-v1/;
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#include "sama5d2.dtsi"
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#include "sama5d2-pinfunc.h"
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/ {
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model = "Atmel SAMA5D2 Xplained";
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compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
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chosen {
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stdout-path = &uart1;
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};
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ahb {
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usb1: ohci@00400000 {
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num-ports = <3>;
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atmel,vbus-gpio = <&pioA 42 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_default>;
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status = "okay";
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};
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usb2: ehci@00500000 {
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status = "okay";
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};
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sdmmc0: sdio-host@a0000000 {
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bus-width = <8>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
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status = "okay";
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};
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sdmmc1: sdio-host@b0000000 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
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status = "okay"; /* conflict with qspi0 */
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};
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apb {
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qspi0: spi@f0020000 {
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status = "okay";
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flash@0 {
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compatible = "atmel,sama5d2-qspi-flash";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0_default>;
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spi-max-frequency = <83000000>;
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partition@00000000 {
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label = "boot";
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reg = <0x00000000 0x00c00000>;
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};
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partition@00c00000 {
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label = "rootfs";
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reg = <0x00c00000 0x00000000>;
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};
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};
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};
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spi0: spi@f8000000 {
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cs-gpios = <&pioA 17 0>, <0>, <0>, <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0_default>;
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status = "okay";
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spi_flash@0 {
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compatible = "spi-flash";
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reg = <0>;
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spi-max-frequency = <50000000>;
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};
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};
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macb0: ethernet@f8008000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
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phy-mode = "rmii";
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status = "okay";
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ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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uart1: serial@f8020000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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status = "okay";
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};
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i2c1: i2c@fc028000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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status = "okay";
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};
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pioA: gpio@fc038000 {
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pinctrl {
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pinctrl_i2c1_default: i2c1_default {
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pinmux = <PIN_PD4__TWD1>,
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<PIN_PD5__TWCK1>;
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bias-disable;
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};
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pinctrl_macb0_phy_irq: macb0_phy_irq {
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pinmux = <PIN_PC9__GPIO>;
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bias-disable;
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};
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pinctrl_macb0_rmii: macb0_rmii {
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pinmux = <PIN_PB14__GTXCK>,
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<PIN_PB15__GTXEN>,
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<PIN_PB16__GRXDV>,
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<PIN_PB17__GRXER>,
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<PIN_PB18__GRX0>,
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<PIN_PB19__GRX1>,
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<PIN_PB20__GTX0>,
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<PIN_PB21__GTX1>,
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<PIN_PB22__GMDC>,
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<PIN_PB23__GMDIO>;
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bias-disable;
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};
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pinctrl_qspi0_default: qspi0_default {
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pinmux = <PIN_PA22__QSPI0_SCK>,
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<PIN_PA23__QSPI0_CS>,
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<PIN_PA24__QSPI0_IO0>,
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<PIN_PA25__QSPI0_IO1>,
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<PIN_PA26__QSPI0_IO2>,
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<PIN_PA27__QSPI0_IO3>;
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bias-disable;
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};
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pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
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pinmux = <PIN_PA1__SDMMC0_CMD>,
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<PIN_PA2__SDMMC0_DAT0>,
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<PIN_PA3__SDMMC0_DAT1>,
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<PIN_PA4__SDMMC0_DAT2>,
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<PIN_PA5__SDMMC0_DAT3>,
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<PIN_PA6__SDMMC0_DAT4>,
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<PIN_PA7__SDMMC0_DAT5>,
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<PIN_PA8__SDMMC0_DAT6>,
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<PIN_PA9__SDMMC0_DAT7>;
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bias-pull-up;
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};
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pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
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pinmux = <PIN_PA0__SDMMC0_CK>,
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<PIN_PA10__SDMMC0_RSTN>,
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<PIN_PA11__SDMMC0_VDDSEL>,
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<PIN_PA13__SDMMC0_CD>;
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bias-disable;
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};
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pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
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pinmux = <PIN_PA28__SDMMC1_CMD>,
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<PIN_PA18__SDMMC1_DAT0>,
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<PIN_PA19__SDMMC1_DAT1>,
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<PIN_PA20__SDMMC1_DAT2>,
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<PIN_PA21__SDMMC1_DAT3>;
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bias-pull-up;
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};
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pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
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pinmux = <PIN_PA22__SDMMC1_CK>,
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<PIN_PA30__SDMMC1_CD>;
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bias-disable;
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};
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pinctrl_spi0_default: spi0_default {
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pinmux = <PIN_PA14__SPI0_SPCK>,
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<PIN_PA15__SPI0_MOSI>,
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<PIN_PA16__SPI0_MISO>;
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bias-disable;
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};
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pinctrl_uart1_default: uart1_default {
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pinmux = <PIN_PD2__URXD1>,
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<PIN_PD3__UTXD1>;
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bias-disable;
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};
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pinctrl_usb_default: usb_default {
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pinmux = <PIN_PB10__GPIO>;
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bias-disable;
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};
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pinctrl_usba_vbus: usba_vbus {
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pinmux = <PIN_PA31__GPIO>;
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bias-disable;
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};
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};
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};
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};
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};
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};
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671
arch/arm/dts/sama5d2.dtsi
Normal file
671
arch/arm/dts/sama5d2.dtsi
Normal file
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@ -0,0 +1,671 @@
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#include "skeleton.dtsi"
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/ {
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model = "Atmel SAMA5D2 family SoC";
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compatible = "atmel,sama5d2";
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aliases {
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spi0 = &spi0;
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spi1 = &qspi0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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usb1: ohci@00400000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@00500000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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clocks = <&utmi>, <&uhphs_clk>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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sdmmc1: sdio-host@b0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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pmc: pmc@f0014000 {
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compatible = "atmel,sama5d2-pmc", "syscon";
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reg = <0xf0014000 0x160>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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#clock-cells = <0>;
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};
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plla: pllack {
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compatible = "atmel,sama5d3-clk-pll";
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#clock-cells = <0>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <12000000 12000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
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};
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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audio_pll_frac: audiopll_fracck {
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compatible = "atmel,sama5d2-clk-audio-pll-frac";
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#clock-cells = <0>;
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clocks = <&main>;
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};
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audio_pll_pad: audiopll_padck {
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compatible = "atmel,sama5d2-clk-audio-pll-pad";
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#clock-cells = <0>;
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clocks = <&audio_pll_frac>;
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};
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audio_pll_pmc: audiopll_pmcck {
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compatible = "atmel,sama5d2-clk-audio-pll-pmc";
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#clock-cells = <0>;
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clocks = <&audio_pll_frac>;
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};
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utmi: utmick {
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compatible = "atmel,at91sam9x5-clk-utmi";
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#clock-cells = <0>;
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clocks = <&main>;
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};
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mck: masterck {
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compatible = "atmel,at91sam9x5-clk-master";
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#clock-cells = <0>;
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clocks = <&main>, <&plladiv>, <&utmi>;
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atmel,clk-output-range = <124000000 166000000>;
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atmel,clk-divisors = <1 2 4 3>;
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};
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h32ck: h32mxck {
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#clock-cells = <0>;
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compatible = "atmel,sama5d4-clk-h32mx";
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clocks = <&mck>;
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};
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usb: usbck {
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compatible = "atmel,at91sam9x5-clk-usb";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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prog: progck {
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compatible = "atmel,at91sam9x5-clk-programmable";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&pmc>;
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clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0: prog0 {
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#clock-cells = <0>;
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reg = <0>;
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};
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prog1: prog1 {
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#clock-cells = <0>;
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reg = <1>;
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};
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prog2: prog2 {
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#clock-cells = <0>;
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reg = <2>;
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};
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};
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systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck: ddrck {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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lcdck: lcdck {
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#clock-cells = <0>;
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reg = <3>;
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clocks = <&mck>;
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};
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uhpck: uhpck {
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#clock-cells = <0>;
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reg = <6>;
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clocks = <&usb>;
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};
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udpck: udpck {
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#clock-cells = <0>;
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reg = <7>;
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clocks = <&usb>;
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};
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pck0: pck0 {
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#clock-cells = <0>;
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reg = <8>;
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clocks = <&prog0>;
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};
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pck1: pck1 {
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#clock-cells = <0>;
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reg = <9>;
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clocks = <&prog1>;
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};
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pck2: pck2 {
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#clock-cells = <0>;
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reg = <10>;
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clocks = <&prog2>;
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};
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iscck: iscck {
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#clock-cells = <0>;
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reg = <18>;
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clocks = <&mck>;
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};
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};
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periph32ck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&h32ck>;
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macb0_clk: macb0_clk {
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#clock-cells = <0>;
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reg = <5>;
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atmel,clk-output-range = <0 83000000>;
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};
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tdes_clk: tdes_clk {
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#clock-cells = <0>;
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reg = <11>;
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atmel,clk-output-range = <0 83000000>;
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};
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matrix1_clk: matrix1_clk {
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#clock-cells = <0>;
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reg = <14>;
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};
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hsmc_clk: hsmc_clk {
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#clock-cells = <0>;
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reg = <17>;
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};
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pioA_clk: pioA_clk {
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#clock-cells = <0>;
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reg = <18>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx0_clk: flx0_clk {
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#clock-cells = <0>;
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reg = <19>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx1_clk: flx1_clk {
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#clock-cells = <0>;
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reg = <20>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx2_clk: flx2_clk {
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#clock-cells = <0>;
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reg = <21>;
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atmel,clk-output-range = <0 83000000>;
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};
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flx3_clk: flx3_clk {
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#clock-cells = <0>;
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reg = <22>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
flx4_clk: flx4_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <23>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart0_clk: uart0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <24>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart1_clk: uart1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <25>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart2_clk: uart2_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <26>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart3_clk: uart3_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <27>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uart4_clk: uart4_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <28>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
twi0_clk: twi0_clk {
|
||||
reg = <29>;
|
||||
#clock-cells = <0>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
twi1_clk: twi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <30>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
spi0_clk: spi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <33>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
spi1_clk: spi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <34>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
tcb0_clk: tcb0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <35>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
tcb1_clk: tcb1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <36>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pwm_clk: pwm_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <38>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
adc_clk: adc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <40>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
uhphs_clk: uhphs_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <41>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
udphs_clk: udphs_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <42>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
ssc0_clk: ssc0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <43>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
ssc1_clk: ssc1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <44>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
trng_clk: trng_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <47>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pdmic_clk: pdmic_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <48>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
i2s0_clk: i2s0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <54>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
i2s1_clk: i2s1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <55>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
can0_clk: can0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <56>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
can1_clk: can1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <57>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
classd_clk: classd_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <59>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
};
|
||||
|
||||
periph64ck {
|
||||
compatible = "atmel,at91sam9x5-clk-peripheral";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mck>;
|
||||
|
||||
dma0_clk: dma0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
dma1_clk: dma1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
aes_clk: aes_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <9>;
|
||||
};
|
||||
|
||||
aesb_clk: aesb_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <10>;
|
||||
};
|
||||
|
||||
sha_clk: sha_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <12>;
|
||||
};
|
||||
|
||||
mpddr_clk: mpddr_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <13>;
|
||||
};
|
||||
|
||||
matrix0_clk: matrix0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <15>;
|
||||
};
|
||||
|
||||
sdmmc0_hclk: sdmmc0_hclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <31>;
|
||||
};
|
||||
|
||||
sdmmc1_hclk: sdmmc1_hclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <32>;
|
||||
};
|
||||
|
||||
lcdc_clk: lcdc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <45>;
|
||||
};
|
||||
|
||||
isc_clk: isc_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <46>;
|
||||
};
|
||||
|
||||
qspi0_clk: qspi0_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <52>;
|
||||
};
|
||||
|
||||
qspi1_clk: qspi1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <53>;
|
||||
};
|
||||
};
|
||||
|
||||
gck {
|
||||
compatible = "atmel,sama5d2-clk-generated";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&main>, <&plla>, <&utmi>, <&mck>;
|
||||
|
||||
sdmmc0_gclk: sdmmc0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <31>;
|
||||
};
|
||||
|
||||
sdmmc1_gclk: sdmmc1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <32>;
|
||||
};
|
||||
|
||||
tcb0_gclk: tcb0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <35>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
tcb1_gclk: tcb1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <36>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pwm_gclk: pwm_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <38>;
|
||||
atmel,clk-output-range = <0 83000000>;
|
||||
};
|
||||
|
||||
pdmic_gclk: pdmic_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <48>;
|
||||
};
|
||||
|
||||
i2s0_gclk: i2s0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <54>;
|
||||
};
|
||||
|
||||
i2s1_gclk: i2s1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <55>;
|
||||
};
|
||||
|
||||
can0_gclk: can0_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <56>;
|
||||
atmel,clk-output-range = <0 80000000>;
|
||||
};
|
||||
|
||||
can1_gclk: can1_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <57>;
|
||||
atmel,clk-output-range = <0 80000000>;
|
||||
};
|
||||
|
||||
classd_gclk: classd_gclk {
|
||||
#clock-cells = <0>;
|
||||
reg = <59>;
|
||||
atmel,clk-output-range = <0 100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qspi0: spi@f0020000 {
|
||||
compatible = "atmel,sama5d2-qspi";
|
||||
reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
|
||||
reg-names = "qspi_base", "qspi_mmap";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&qspi0_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@f8000000 {
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xf8000000 0x100>;
|
||||
clocks = <&spi0_clk>;
|
||||
clock-names = "spi_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
macb0: ethernet@f8008000 {
|
||||
compatible = "cdns,macb";
|
||||
reg = <0xf8008000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&macb0_clk>, <&macb0_clk>;
|
||||
clock-names = "hclk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@f8020000 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xf8020000 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8028000 {
|
||||
compatible = "atmel,sama5d2-i2c";
|
||||
reg = <0xf8028000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi0_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sckc@f8048050 {
|
||||
compatible = "atmel,at91sam9x5-sckc";
|
||||
reg = <0xf8048050 0x4>;
|
||||
|
||||
slow_rc_osc: slow_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-accuracy = <250000000>;
|
||||
atmel,startup-time-usec = <75>;
|
||||
};
|
||||
|
||||
slow_osc: slow_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_xtal>;
|
||||
atmel,startup-time-usec = <1200000>;
|
||||
};
|
||||
|
||||
clk32k: slowck {
|
||||
compatible = "atmel,at91sam9x5-clk-slow";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_rc_osc &slow_osc>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@fc000000 {
|
||||
compatible = "atmel,at91rm9200-spi";
|
||||
reg = <0xfc000000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@fc028000 {
|
||||
compatible = "atmel,sama5d2-i2c";
|
||||
reg = <0xfc028000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi1_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pioA: gpio@fc038000 {
|
||||
compatible = "atmel,sama5d2-gpio";
|
||||
reg = <0xfc038000 0x600>;
|
||||
clocks = <&pioA_clk>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
pinctrl {
|
||||
compatible = "atmel,sama5d2-pinctrl";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user