Commit Graph

34336 Commits

Author SHA1 Message Date
York Sun
da305b9f57 drivers/ddr/fsl: Fix typo in BIST test for DDR4
BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-11-30 09:11:12 -08:00
Alison Wang
d764129d30 armv8/layerscape: Update MMU table with execute-never bits
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
2015-11-30 09:11:11 -08:00
York Sun
61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
7023100971 armv8/ls1043ardb: add USB support
Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
28752cf83b armv8/ls1043ardb: add DSPI support
Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
630532f51f armv8/ls1043aqds: dts: add dtb support
Reuse the dts files from ls1043a linux kernel.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Shaohui Xie
02b5d2ed86 armv8/ls1043aqds: add LS1043AQDS board support
LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Gong Qianyu
e1cecb4d42 armv8/ls1043ardb: dts: add dtb support
Reuse dts files from ls1043a linux kernel. Some parts in dts files
may not be needed by U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Gong Qianyu
18a0d8eb46 armv8/fsl-layerscape: Remove reference to gdata
The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Mingkai Hu
af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Prabhakar Kushwaha
14480454c7 driver: net: ldpaa: Fix Rx buffer alignment
MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"

Updating the DPNI Eth driver to comply with the restriction.

Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
5038d3e5f2 driver: net: ldpaa: Add debug information
Add following debug information in the driver
 - Get various DPNI counter values
 - Get link status of DPNI objects
 - Get information of both ends of connection (DPMAC - DPNI)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
c919ab9ee5 driver: net: ldpaa: Use DPMAC as net device
As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.

Use DPMAC as net device where it represents physical lane.
Below modification done in driver
 - Use global DPNI object
 - Connect DPMAC to DPNI
 - Create and destroy DPMAC

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
1730a17db9 driver: net: fsl-mc: Create DPAA2 object at run-time
Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.

Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
fb4a87a737 driver: net: fsl-mc: Add DPAA2 commands to manage MC
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.

Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
553d2751c1 driver: net: fsl-mc: Increase MC command timeout
dpni_create API take takes more time as comapred to existing supported
APIs of MC Flib.
So increase MC command timeout.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
f9127a046d driver: ldpaa: Add api to return linked PHY ID of DPMAC
DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.

So Add an api to return linked PHY ID of DPMAC object.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
25af413740 armv8: ls2085aqds: Print function name during SerDes error
Print function name along with SerDes Protocol during SerDes Protocol
not supported error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
872d48a777 driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
1ebbe4fcf7 driver: net: fsl-mc: Add create, destroy APIs in flibs
Current Management Complex Flibs does not support APIs for adding and
destroying the objects.

Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
99e904c1f0 armv8: lsch3: Fix lane protocol parsing logic
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.

Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Alison Wang
a1399534f1 arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS
This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot,but the problem was mysteriously related to the toolchain
used for building u-boot.Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.This causes the timer compare to fire 344 seconds
after u-boot configures it.Depending on how fast u-boot gets the
kernel booted,this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.

To fix the above issue, the generic physical timer is disabled
before jumping to the OS.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:01 -08:00
Alison Wang
2b714cfad4 arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit
This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot.  Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.  This causes the timer compare to fire 344 seconds
after u-boot configures it.  Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains.  Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:01 -08:00
Tom Rini
2a8696dfc2 Merge git://git.denx.de/u-boot-socfpga 2015-11-30 08:30:14 -05:00
Chin Liang See
486f4fa98c arm: socfpga: Remove fsloadcmd from environment
Remove fsloadcmd / ext2load as we are using load command
which use the corresponding latest file system command.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-11-30 13:30:19 +01:00
Chin Liang See
271e9ecd72 arm: socfpga: dts: Adding drvsel and smplsel to dts
Adding new node drvsel and smplsel for SDMMC

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2015-11-30 13:30:19 +01:00
Chin Liang See
9a41404dc6 mmc: socfpga_dw_mmc: Move drvsel and smplsel to dts
socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-30 13:30:19 +01:00
Marek Vasut
856b30dae5 arm: socfpga: Repair SoCrates board
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-30 13:30:19 +01:00
Dinh Nguyen
871c24bc50 ARM: socfpga: rename the cyclone5 and arria5 base address file
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.

Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-30 13:30:19 +01:00
Dinh Nguyen
5a7152e4fd ARM: socfpga: arria10: add base address map for Arria10
Add the base address map for Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-30 13:30:19 +01:00
Philipp Rosenberger
8a30e3a73a arm: socfpga: reset: FIX address of tstscratch register
The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.

Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map

Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
2015-11-30 13:30:19 +01:00
Tom Rini
60e12b3a71 Merge git://www.denx.de/git/u-boot-cfi-flash 2015-11-30 07:11:53 -05:00
Tom Rini
30f56399e7 Merge git://www.denx.de/git/u-boot-ppc4xx 2015-11-30 07:10:49 -05:00
Tom Rini
a71d99ac03 Merge branch 'master' of git://git.denx.de/u-boot-samsung 2015-11-30 07:10:27 -05:00
Tom Rini
c1924d85af Merge branch 'master' of git://git.denx.de/u-boot-video 2015-11-30 07:10:18 -05:00
Thomas Chou
5aeeabf43c cfi_flash: give default CONFIG_SYS_MAX_FLASH_SECT in flash.h
Give default CONFIG_SYS_MAX_FLASH_SECT in flash.h, so that
the header can be included regardless of the present of flash.
The value 512 is the most used.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
2015-11-30 13:00:00 +01:00
Wolfgang Denk
6623aee5b6 PPC4xx: Create "liebherr" vendor directory
In preparation of some new Liebherr boards to be added soon, a new
"liebherr" vendor directory gets created, and the "lwmon5" board
directory is moved into this new vendor directory.

cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2015-11-30 12:50:29 +01:00
Stefan Roese
7514037bcd ppc4xx: Remove remnants from ocotea, taishan, ebony and taihu
The removal of some PPC4xx boards did not catch all references to
these boards. This patch now removes all remnants still left.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
2015-11-30 12:44:54 +01:00
Peng Fan
3dbdb4dd4f video: ipu: fix out of bounds access
We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2].
If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds
the size of stp_rep array.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Liu Ying <Ying.Liu@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
2015-11-30 09:18:36 +01:00
Minkyu Kang
225f5eeccd arm: s5pc1xx: move SoC to mach-s5pc1xx
move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-30 17:17:01 +09:00
Gerald Kerma
f1df81c400 arm: kirkwood: add ZyXEL NSA310S device
This patch add ZyXEL NSA310S 1-Bay Media Server

The ZyXEL NSA310S device is a Kirkwood based NAS:

- SoC: Marvell 88F6702 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 4 Status LED (green)
- 1 Copy/Sync button
- 1 Reset button
- 1 SATA II port
- 2 USB 2.0 ports (front and back)
- Smart fan

Signed-off-by: Gerald Kerma <dreagle@doukki.net>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Luka Perkov <luka.perkov@sartura.hr>
2015-11-29 22:16:14 +01:00
Reinhard Pfau
76b391cdee tools/kwbimage: fix size computations for v1 images
Fix computation of haeder size and binary header size.
Size of opt header and some 32bit values were not taken into account. This could
result in invalid boot images (due to the wrong binary header size, the image could
claim to have another extension header after the binary extension although there
is none).

Use "uint32_t" instead of "unsigned int" for header size computation.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-29 16:02:44 +01:00
Reinhard Pfau
a8840dced0 tools/kwbimage: fix endianess issue
KWB image header values are in little endian (LE).
So adding appropriate cpu_to_leXX() calls to allow building those images
on BE hosts, too.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-11-29 16:02:44 +01:00
Stefan Roese
7772085930 tools/kwbimage.c: Make sure that the resulting image is 4-byte aligned
With the dtb added to the main U-Boot image, it can happen, that
the resulting image is not 4-byte aligned. As the dtb tends to
be unaligned. But the image needs to be 4-byte aligned. At least the
Marvell hdrparser tool complains if its unaligned. By returning 1 here
in kwbimage_generate(), called via tparams->vrec_header() in mkimage.c,
mkimage will automatically pad the resulting image to a 4-byte size
if necessary.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-11-29 16:02:44 +01:00
Stefan Roese
9eb14cc443 arm: mvebu: Configure ARP timeout and retry count
As some MVEBU platforms using the MVNETA driver seem to miss the
first ARP packet, lets reduce the timeout and increase the retry
count. This increases the speed for communication establishment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-11-29 16:02:44 +01:00
Tom Rini
fa8883a1e3 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2015-11-27 08:41:03 -05:00
Stefan Roese
a06728c839 i2c: Fix the comment to match the function described
Use the correct function name in the function description.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
2015-11-27 05:54:21 +01:00
Stefan Roese
01ce961b15 arm: spear: x600: Enable tiny-printf
Enabling the new tiny-printf function makes the SPL image fit again in
the 8KiB restricted area.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
2015-11-25 10:06:45 -05:00