Currently when we define CONFIG_SERIAL_TAG we will barf with a failure to
define "struct tag_serialnr".
This structure is defined in <asm/setup.h>, this patch includes
<asm/setup.h> to fix.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
When the DDR calibration is enabled, a situation may happen that it
will fail on a few select boards out of a whole production lot. In
particular, after the first write leveling stage, the MPWLDECTRLx
registers will contain a value 0x1nn , for nn usually being 0x7f or
slightly lower.
What this means is that the HW write leveling detected that the DQS
rising edge on one or more bundles arrives slightly _after_ CLK and
therefore when the DDR DRAM samples CLK on the DQS rising edge, the
CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18).
The HW write leveling then ends up adding almost an entire cycle (thus
the 0x17f) to the DQS delay, which indeed aligns it, but also triggers
subsequent calibration failure in DQS gating due to this massive offset.
There are two observations here:
- If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the
DQS gating passes, the entire calibration passes as well and the
DRAM is perfectly stable even under massive load.
- When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so
in MPWLDECTRx register is not there, but it is replaced by 0x0 as one
would expect.
Someone from NXP finally explains why, quoting [1]:
"
Having said all that, the DDR Stress Test does something that we
do not advertise to the users. The Stress Test iself looks at the
values of the MPWLDECTRL0/1 fields before reporting results, and
if it sees any filed with a value greater than 200/256 delay
(reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR
Stress test will reset the Write Leveling delay for this lane
to 0x000 and not report it in the log.
The reason that the DDR Stress test does this is because a delay
of more than 78% a clock cycle means that the DQS edge is arriving
within the JEDEC tolerence of 25% of the clock edge. In most cases,
DQS is arriving < 5% tCK of the SDCLK edge in the early case, and
it does not make sense to delay the DQS strobe almost a full clock
cycle and add extra latency to each Write burst just to make the
two edges align exactly. In this case, we are guilty of making a
decision for the customer without telling them we are doing it so
that we don't have to provide the above explanation to every customer.
They don't need to know it.
"
This patch adds the correction described above, that is if the MPWLDECTRx
value is over 0x148, the value is corrected back to 0x0.
[1] https://community.nxp.com/thread/456246
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Similarly to imx6, before reading the boot device, first check
bmode to see if the serial downloader has been selected
explicitly, then check whether the serial downloader has been
activated due to unbootable primary boot devices (e.g. empty eMMC).
If the serial downloader is activated, return BOOT_DEVICE_BOARD.
This allows SPL with SDP support to wait for the U-Boot image
to be loaded via the serial download protocol using imx_usb_loader.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
The i.MX6ULL has a WDOG3 located at start address 0x021E0000 in the
AIPS-2 memory region [1].
[1] i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017,
Table 2-3. AIPS-2 memory map, p. 178
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The i.MX6UL has a WDOG3 located at start address 0x021E0000 in the
AIPS-2 memory region [1].
[1] i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1,
04/2016, Table-2-3 AIPS-2 memory map, p. 166
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
HW accelerated "hash sha256 ..." command doesn't work on i.MX6UL, we get
"CAAM was not setup properly or it is faulty" error message.
This is due to wrong CAAM base 0x02100000, on i.MX6UL the CAAM base
address is 0x02140000. Fix it.
Note: with this patch applied the "hash sha256" commant still has some
issues on i.MX6UL ("Invalid KEY Command" or other errors). With data
cache off the "hash sha256" command works as expected.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
NXP layerscape platforms like ls1088a, ls2088a
uses MXC I2C Controller.
-Remove dependency of MX6 for the same.
Update related configs to use Kconfig file.
-Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
commit ed286bc80e ("imx: hab: Check if CSF is valid before authenticating
image") makes use of "__packed" as a prefix to the "struct hab_hdr"
declaration.
With my compiler "gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)" we
get:
./arch/arm/include/asm/mach-imx/hab.h:42:25: error: expected ‘=’, ‘,’, ‘;’,
‘asm’ or ‘__attribute__’ before ‘{’ token
struct __packed hab_hdr {
Fix this problem by including <linux/compiler.h>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This patch fixes the wrongly included dtsi file which was
breaking mainline support for Engicam i.CoreM6 DualLite/Solo RQS.
Linux commit details for the same change as
"ARM: dts: imx6dl: Include correct dtsi file for Engicam i.CoreM6
DualLite/Solo RQS"
(sha1: c0c6bb2322964bd264b4ddedaa5776f40c709f0c)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
usdhc4 node need to update pinctrl, bus-width and non-removable
properties, sync the same from Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Without the volatile attribute, compilers are entitled to optimize out
the same asm(). In the case of __udelay() in syscounter.c, it calls
`get_ticks()` twice, one for the starting time and the second in the
loop to check the current time. When compilers inline `get_ticks()`
they see the same `mrrc` instructions and optimize out the second one.
This leads to infinite loop since we don't get updated value from the
system counter.
Here is a portion of the disassembly of __udelay:
88: 428b cmp r3, r1
8a: f8ce 20a4 str.w r2, [lr, #164] ; 0xa4
8e: bf08 it eq
90: 4282 cmpeq r2, r0
92: f8ce 30a0 str.w r3, [lr, #160] ; 0xa0
96: d3f7 bcc.n 88 <__udelay+0x88>
98: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
Note that final jump / loop at 96 to 88, we don't have any `mrrc`.
With a volatile attribute, the above changes to this:
8a: ec53 2f0e mrrc 15, 0, r2, r3, cr14
8e: 42ab cmp r3, r5
90: f8c1 20a4 str.w r2, [r1, #164] ; 0xa4
94: bf08 it eq
96: 42a2 cmpeq r2, r4
98: f8c1 30a0 str.w r3, [r1, #160] ; 0xa0
9c: d3f5 bcc.n 8a <__udelay+0x8a>
9e: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
a2: bf00 nop
I'm advised[1] to put volatile on all asm(), so this commit also adds it
to the asm() in timer_init().
[1]: https://lists.denx.de/pipermail/u-boot/2018-March/322062.html
Signed-off-by: Yasushi SHOJI <yasushi.shoji@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Rename CONFIG_SPL_USBETH_SUPPORT to CONFIG_SPL_USB_ETHER.
This enables users to block text using CONFIG_IS_ENABLED() instead
of resorting to #if ladders with SPL and non-SPL cases.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
This patch got dropped during the update of DTs to 4.14, re-add it
back. This adds reset GPIOs to the ethernet PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
These do not need to be available early on Gen3 , so move them to
the respective DT files.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add R8A77965 M3N Salvator-XS development kit support. This kit is
similar to the other Salvator-X(S) ones, except is has M3N SoC on
it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add SDHI nodes to r8a77965.dtsi to get eMMC and SD slots operational.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add xHCI node to r8a77965.dtsi to get xHCI USB operational.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add generic EHCI nodes to r8a77965.dtsi to get EHCI USB operational.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add RAVB node to r8a77965.dtsi to get ethernet operational.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Import the R8A77965 M3N DT from Linux 4.16-rc1 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch added Kconfig support for CONFIG_ZYNQ_SDHCI_MAX_FREQ
and enabled it in respective defconfig.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Replace the placeholder DTS for R8A7790 H2 Stout with a proper
DTS from Linux next .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add support for a new boards from devboards.de , the DBM-SoC1 .
This board has one ethernet port, one USB OTG port and USB UART.
Signed-off-by: Marek Vasut <marex@denx.de>
The area for struct mmc can be allocated dynamically. It greatly reduces
the size of struct omap_hsmmc_plat. This is useful in cases where the board
level code declares one or two struct omap_hsmmc_plat because it doesn't
use the Driver Model.
This saves around 740 bytes for the am335x_evm SPL.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit d695d66278 ("spl: eMMC/SD: Provide one __weak spl_boot_mode()
function") breaks the boot on several i.MX6 boards,
such as cuboxi and wandboard:
U-Boot SPL 2018.03-rc1-00212-g48914fc119 (Feb 10 2018 - 11:04:33 +1300)
Trying to boot from MMC1
Failed to mount ext2 filesystem...
spl_load_image_ext: ext4fs mount err - 0
Partially revert it so that we can boot U-Boot again on these
i.MX6 platforms.
Reported-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
TPL offset 0xff704004 is unaligned address which is adding nearest
8-bytes for next instruction, So 0xff704004 is adding 0x20 for
proper alignment which is causing the next instruction data
0xefffffff is moved.
Hexdump with overlaped bytes:
-----------------------------
0000000 0000 0000 0000 0000 0000 0000 0000 0000
0000010 0000 0000 0000 0000 0000 0000 ffff eaff
So, Fix the TEXT_BASE for proper aligned address 0xff704000
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Due to size limitations in SPL by adding falcon mode,
rk3288 support TPL. In order to not overlap SPL_TEXT_BASE
add TPL_TEXT_BASE with u-boot-tpl.lds that intern call
u-boot-spl.lds with proper TEXT_BASE values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
usdhc4 has eMMC on icore-rqs boards, SPL is not detecting
it becuase of u-boot,dm-spl flag so add it to make eMMC working.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
These were dropped in [1], after relocation, for their values offset by
reloc_off.
Unconditionally show the HW values and add a '(reloc)' hint for the
offset values showed after relocation.
Also, the LRs' dumps are now formatted the same way the other regs' are.
[1] Commit 082693f4 ("arm64 :show_regs: show the address before relocation")
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
TI_SECURE_DEVICE is used by both OMAP2+ and Keystone2 family devices,
and so when ARCH_OMAP2PLUS was used to gate off the OMAP2+ Kconfig
Keystone2 family devices lost this config option.
Move this option out of mach-omap2 Kconfig to a spot accessible by both
families. We picked arch/arm/Kconfig over the TI specific board/ti/
location as this option is not specific to our boards but rather our
architecture.
Plus at some point this option can be changed to just
SECURE_DEVICE, as having secure parts is not exclusive to TI and
so other vendors can interpret this option as needed by their device
configurations.
Fixes: a93fbf4a78 ("ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate Kconfig")
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently SPL_LOAD_FIT is unable to boot from nand on
i.MX6QDL platform, so enable only for MMC boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Engicam Is.IoT has eMMC and NAND cpu modules where MMC
is common for both, so remove explicit mmc defconfig.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Currently the following devices are using a different definition for ROM
Vector Table addresses:
- i.MX6DQP = All rev
- i.MX6DQ >= rev 1.5
- i.MX6SDL >= rev 1.2
There is no need to create a new RVT macros since the only update were the
RVT base address. Remove HAB_RVT_*_NEW macros and define a new RVT base
address.
More details about RVT base address can be found on processors Reference
Manual and in the following documents:
EB803: i.MX 6Dual/6Quad Applications Processor Silicon Revision 1.2 to 1.3
Comparison
EB804: i.MX 6Solo/6DualLite Application Processor Silicon Revision 1.1
to 1.2/1.3 Comparison
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Write, Check and Set MID commands have been deprecated from the Code
Signing Tool (CST) v2.3.3 and will not be implemented in newer versions
of HAB, hence the following features are no longer available:
- Write Data
- Clear Mask
- Set Mask
- Check All Clear
- Check All Set
- Check Any Clear
- Check Any Set
- Set MID
The inappropriate use of Write Data command may lead to an incorrect
authentication boot flow. Since no specific application has been identified
that requires the use of any of these features, it is highly recommended to
add this check.
Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
For proper authentication the HAB code must check if the CSF is valid.
Users must call the csf_is_valid() function to parse the CSF prior to
authenticating any additional images. The function will return a failure
if any of the following invalid conditions are met:
- CSF pointer is NULL
- CSF Header does not exist
- CSF does not lie within the image bounds
- CSF command length zero
Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
DCD commands should only be present in the initial boot image loaded by
the SoC ROM. DCD should not be present in images that will be verified
by software using HAB RVT authentication APIs. Newer versions of HAB
will generate an error if a DCD pointer is present in an image being
authenticated by calling the HAB RVT API. Older versions of HAB will
process and run DCD if it is present, and this could lead to an incorrect
authentication boot flow.
It is highly recommended this check is in place to ensure additional HAB
verified images do not include a DCD table.
Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Currently it is not possible to run CMD_DEK on i.MX SPL targets:
=> dek_blob 0x12000000 0x12001000 128
The system hangs after running dek_blob because the CAAM clock is being
disabled by the HAB code. There is no need to disable CAAM clock after
authenticating additional boot images, thus keep CAAM clock enabled to
address this issue.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The UHS modes are not supported in beagle-x15 because it's not possible to
switch the IO lines supply voltage to 1.8v.
Also HS200 cannot be supported on mmc2, because the IO lines of mmc2 are
connected to 3.3v.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>